SMI Handler Update Without Platform Reset
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Solution Overview
Problem
Updating BIOS and SMI handlers in data center and cloud environments requires system resets, leading to costly downtime and potential service level agreement breaches due to the need for platform resets.
Innovation Solution
Implementing a method to update or modify SMI handlers without platform resets by securely adding a second SMI handler in a different region of SMRAM, allowing for seamless switching between handlers, authentication, and rollback capabilities, thus avoiding reboot requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BIOS and SMI handler are updated using conventional methods, then the system can receive security patches and bug fixes, but the system requires a platform reset which causes downtime
Solution Approach 1:
The patent segments the SMI handler into multiple versions stored in different regions of SMRAM (first SMI handler region and second SMI handler region). This allows the system to maintain the current handler while storing updates separately, enabling updates without resetting the platform. The segmentation principle resolves the contradiction by allowing concurrent existence of multiple handler versions without requiring exclusive access during updates.
Solution Approach 2:
The patent implements preliminary action by storing the updated SMI handler code in the second SMI handler region before actually using it. The update process prepares the new handler in advance in a separate region, then switches to it when needed. This preliminary preparation allows the system to update handlers without interrupting current operations, eliminating the need for platform resets during the update process.
2Device complexity
If a single SMI handler is used, then the system structure is simple, but the system cannot perform seamless updates without rebooting
Solution Approach 1:
The patent divides the SMI handler functionality into separate regions within SMRAM - a first SMI handler region for the current active handler and a second SMI handler region for updates. This segmentation maintains relative structural simplicity while enabling update capability, as each region contains a complete but independent handler implementation.
Solution Approach 2:
The patent introduces dynamic switching capability between different SMI handler versions by modifying the SMI handler selection mechanism. Instead of a static single handler, the system can dynamically switch between the first and second SMI handler regions based on update status and operational requirements, providing adaptability without significant complexity increase.
3Reliability
If platform reset is performed for BIOS update, then the new BIOS can be activated, but service availability is compromised
Solution Approach 1:
The patent segments the BIOS update process into two independent phases: (1) downloading and storing the updated BIOS image in the second SMI handler region, and (2) activating the updated BIOS by switching from the first to second region. This segmentation allows the update to be prepared and activated without requiring platform reset, maintaining service availability throughout the process.
Solution Approach 2:
The patent enables continuous operation during BIOS updates by maintaining the ability to switch between handler regions without platform reset. The useful action of running the SMI handler continues uninterrupted, while updates are applied in the background. This continuity principle resolves the contradiction by eliminating the platform reset step that would otherwise interrupt service availability.
Data Source
AI summary
Examples described herein provide a central processing unit (CPU) to reserve a region of memory for use to store both a boot firmware code and a second boot firmware code and to perform the second boot firmware code without reboot. The reserved region of memory can be a region that is not configured for access by an operating system (OS). The reserved region of memory comprises System Management Random Access Memory (SMRAM). If a first interrupt handler is not overwritten after a second boot firmware code is stored, the CPU can roll back to use of the first interrupt handler.


