Real-Time Memory Fault Detection via SMI Stress Tests
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Solution Overview
Problem
Information handling systems, particularly consumer devices, lack real-time memory fault detection and correction capabilities, leading to potential data corruption and system downtime due to unaddressed memory defects, especially in non-ECC memory platforms.
Innovation Solution
The method involves performing a memory stress test during system management interrupts (SMIs) when the processor is idle, detecting defective memory portions, and applying repairs using post-package repair (PPR) support to restore memory functionality without disrupting system operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory stress tests are performed frequently to detect defects early, then reliability is improved, but system productivity deteriorates due to memory unavailability during testing
Solution Approach 1:
The patent implements periodic memory stress tests triggered by system management interrupts (SMIs) that occur during processor idle states. This periodic testing approach allows the system to balance reliability monitoring with operational availability, as tests are performed only when the processor is not actively using memory resources.
Solution Approach 2:
The patent performs memory stress tests as preliminary actions during idle periods before actual memory failures occur. By proactively testing memory during SMIs and idle states, the system identifies and repairs defects before they cause data corruption or system failures, improving reliability without impacting productivity during active operations.
2Reliability
If ECC memory is used to provide real-time error correction, then reliability is improved, but device complexity increases due to additional parity bits and registers
Solution Approach 1:
The patent implements a self-service memory testing and repair system that operates autonomously during processor idle states. The system automatically performs stress tests, detects defects, and applies repairs through post-package repair (PPR) support without requiring complex ECC hardware or external intervention, thereby achieving reliability improvement with minimal added complexity.
Solution Approach 2:
The patent uses software-based stress test algorithms and PPR repair mechanisms instead of expensive ECC hardware. The approach employs disposable test patterns and repair mappings that can be regenerated as needed, providing cost-effective error detection and correction without the permanent overhead of ECC parity bits and registers.
3Measurement precision
If comprehensive memory testing is performed to identify all faulty cells, then measurement precision is improved, but loss of time increases due to extensive testing duration
Solution Approach 1:
The patent performs partial memory testing by targeting specific memory regions that are identified as candidates for defects based on stress test patterns. Rather than testing the entire memory space exhaustively, the system applies excessive stress to specific areas during idle periods, achieving high measurement precision for faulty cell identification with reduced overall testing time.
Solution Approach 2:
The patent replaces traditional mechanical memory testing methods with software-based stress test algorithms executed during SMIs. This substitution allows for rapid, repeated testing of memory regions without the time constraints of physical testing equipment, enabling comprehensive fault identification over time without requiring long continuous test periods.
Data Source
AI summary
Defective memory may cause expensive and unnecessary replacements of the memory especially for higher density dynamic random access memory that has ever shrinking topologies. Running memory stress tests in the background for a period of time at set intervals while the operating system is idle may detect and identify memory problems in real-time without requiring a re-boot of the information handling system. The memory defects may be repaired in real-time so as not to cause loss of data by future read or write requests to the identified defective memory.