SMI Notification Signal Lines for South Bridge Responsivity
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Solution Overview
Problem
The existing interrupt handling techniques in personal computers, particularly with SMI signals, face degraded responsivity due to the embedded controller's low-speed system bus connection, which hinders timely determination of SMI events caused by multifunctional devices like the embedded controller and south bridge.
Innovation Solution
The implementation of dedicated SMI event occurrence notification signal lines between the embedded controller/KBC and the south bridge allows for rapid determination of SMI causes by accessing the south bridge via a high-speed bus, eliminating the need for direct access to the embedded controller, thereby enhancing SMI processing responsiveness without adding new hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the embedded controller is connected to a low-speed system bus, then the system structure is simplified, but the SMI processing responsivity is degraded
Solution Approach 1:
The patent segments the SMI notification path into two independent channels: a high-speed path through the south bridge for time-critical SMI events, and maintains the existing low-speed path through the embedded controller for other purposes. This segmentation allows SMI processing to occur rapidly without requiring the embedded controller to be connected via high-speed bus, thus resolving the contradiction between speed and device complexity.
2Measurement precision
If the BIOS accesses the embedded controller to determine SMI causes, then all SMI events can be identified, but the processing time increases due to low-speed bus access
Solution Approach 1:
The south bridge acts as an intermediary that receives SMI notification signals directly from the embedded controller via a dedicated high-speed notification line. When an SMI event occurs, the south bridge can immediately identify the cause and trigger SMI processing without requiring the BIOS to access the embedded controller through the low-speed system bus, thus maintaining measurement precision while reducing processing time.
3Speed
If the south bridge determines SMI events directly, then SMI processing speed is improved, but the south bridge must have additional determination capabilities
Solution Approach 1:
The patent extracts the SMI cause determination function from the embedded controller and transfers it to the south bridge. The embedded controller sends only the SMI notification signal and cause identification information to the south bridge via a dedicated high-speed line, allowing the south bridge to determine SMI events rapidly without requiring the embedded controller to maintain complex determination capabilities, thus improving speed while managing device complexity.
Data Source
AI summary
An information processing apparatus includes: a CPU; a controller including a signal transmission unit configured to supply an SMI (system management interrupt) signal to the CPU; a multifunctional device having a plurality of functions each potentially causing an SMI; and a plurality of signal lines provided between the controller and the multifunctional device. Each of the signal lines corresponds to one of the plurality of functions and is configured to send a notification of occurrence of an SMI event from the multifunctional device to the controller.