Smooth Via Side Walls via Post-Etch Plasma Scallops Removal
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Solution Overview
Problem
Conventional silicon etching processes, such as the Bosch process, result in the formation of scallops on the side walls of vias due to their isotropic nature, which are difficult to completely eliminate and can compromise the integrity and smoothness of the via walls, leading to suboptimal semiconductor performance.
Innovation Solution
A post-processing method involving specific gas flows and operating biases in a plasma processing chamber is used to selectively remove scallops from the via side walls, utilizing gases like NF3, CF4, and Ar, with pressures and biases optimized to remove the peaks of the scallops without affecting the troughs or increasing the via diameter, thereby achieving a smooth-walled via.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional Bosch etching process is used to create deep vias, then the etching depth and via formation are achieved, but scallops are formed on the side walls reducing manufacturing precision
Solution Approach 1:
The patent implements a periodic etching process that alternates between etching steps and protective layer deposition steps. During etching steps, silicon is removed vertically; during deposition steps, a protective layer is formed on the side walls to prevent lateral etching. This periodic alternation allows deep via formation while minimizing scallop formation, as the protective layer is removed only at the bottom between cycles, maintaining side wall smoothness throughout the process.
2Length of moving object
If multiple etching cycles are performed to achieve deep via formation, then the via depth is increased, but the processing time increases and more scallops are formed
Solution Approach 1:
The patent uses periodic alternation between etching and protective layer deposition to achieve deep via formation efficiently. Each cycle etches a portion of the way down and deposits protection on the sides, allowing subsequent cycles to proceed faster without creating additional scallops. This periodic approach reduces total processing time compared to conventional methods while maintaining the required via depth.
Solution Approach 2:
The protective layer is deposited in advance on the side walls before subsequent etching cycles begin. This preliminary protective action prevents lateral etching and scallop formation during later, deeper etching steps, allowing faster processing without sacrificing side wall quality as the via depth increases.
3Speed
If the etching process is made more aggressive to reduce processing time, then the etching speed increases, but lateral etching increases creating larger scallops
Solution Approach 1:
The patent alternates between aggressive etching steps and protective layer deposition steps. During etching steps, high-speed vertical etching is performed; during deposition steps, the protective layer is formed to prevent lateral etching. This periodic alternation allows aggressive etching parameters to be used without creating large scallops, as the protective layer is removed only at the bottom between cycles, maintaining side wall profile precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively eliminates scallops, ensuring smooth-walled vias with reduced processing time and minimizing undercutting, compared to previous methods, thereby enhancing semiconductor performance and maintaining the integrity of the via dimensions.
Implementation Method 1
the portion of silicon layer 100 that is exposed through window 106 has been etched so as to create via 108. Via 108 is created by generating an etching gas plasma in the etching chamber
Implementation Method 2
Protective layer 116 is disposed upon both a top surface 114 of photoresist mask 104, side wall 110 and bottom surface 112 of via 108. Protective layer 116 may include a polymer that decreases lateral etching
Implementation Method 3
A post-processing method involving specific gas flows and operating biases in a plasma processing chamber is used to selectively remove scallops from the via side walls
Data Source
AI summary
A method is provided for etching silicon in a plasma processing chamber, having an operating pressure and an operating bias. The method includes: performing a first vertical etch in the silicon to create a hole having a first depth and a sidewall; performing a deposition of a protective layer on the sidewall; performing a second vertical etch to deepen the hole to a second depth and to create a second sidewall, the second sidewall including a first trough, a second trough and a peak, the first trough corresponding to the first sidewall, the second trough corresponding to the second sidewall, the peak being disposed between the first trough and the second trough; and performing a third etch to reduce the peak.