Smoothing Capacitor Layout for Low-Inductance Semiconductor Modules
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Solution Overview
Problem
In semiconductor devices, particularly those using wide bandgap semiconductors like SiC-MOSFET, the capacitance of smoothing capacitors needs to be significantly large to handle high currents, but this requires a large physical space and increases wiring inductance when located above the semiconductor element, making it difficult to reduce inductance effectively.
Innovation Solution
The smoothing capacitor is positioned non-overlapping with the semiconductor element and directly connected to the circuit pattern via a bonding interface, eliminating the need for screws and allowing a shorter wiring length, thereby reducing wiring inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the smoothing capacitor is located on the upper side of the semiconductor element to reduce wiring distance, then the wiring inductance is reduced, but the device size increases and insulation distance requirements cannot be met
Solution Approach 1:
The patent transitions from a vertical stacking arrangement (capacitor above semiconductor element) to a lateral planar arrangement (capacitor beside semiconductor element). This dimensional change allows the capacitor to be positioned in the lateral direction rather than vertically above, reducing the required vertical space while maintaining acceptable wiring length and inductance characteristics.
Solution Approach 2:
The patent divides the device into distinct functional regions: a first region for the semiconductor element and a second region for the smoothing capacitor, separated by an insulating substrate. This segmentation allows independent optimization of each component's position and reduces interference between them, enabling the capacitor to be placed laterally without compromising insulation requirements.
2Power
If the capacitance of the smoothing capacitor is increased to handle large current, then the current handling capability is improved, but the physical space required increases making it difficult to house within the device
Solution Approach 1:
The patent employs a composite structure combining an aluminum electrolytic capacitor with a specific can-shaped housing and integrated terminal structure. This composite design optimizes the capacitor's space utilization, allowing high capacitance values (several hundred μF) to be achieved while maintaining a compact form factor that can be laterally positioned next to the semiconductor element.
Solution Approach 2:
By positioning the high-capacitance capacitor laterally in the second region rather than vertically above the semiconductor element, the patent accommodates the increased capacitor volume in the lateral dimension. This spatial redistribution allows the device to house large-capacitance components without increasing the vertical footprint or compromising the semiconductor element's positioning.
3Reliability
If the aluminum electrolytic capacitor is electrically connected using a wiring plate and screw for fixing, then the connection is secure, but the inductance increases due to the extended wiring path
Solution Approach 1:
The patent removes the intermediate wiring plate and screw connection components from the electrical connection path between the capacitor and the circuit board. By establishing a direct electrical connection between the capacitor terminal and the circuit board pad, the design extracts out the unnecessary intermediate elements that contributed to increased inductance, while maintaining secure mechanical and electrical connection.
Solution Approach 2:
The patent replaces the mechanical screw-fixed wiring plate connection system with a direct bonding or soldering connection system. This substitution eliminates the multi-component mechanical assembly (screw, wiring plate, terminal) and uses a more direct electrical connection method that reduces the current path length and associated inductance while maintaining connection reliability.
Data Source
AI summary
Provided is a technique capable of reducing wiring inductance of a smoothing capacitor. A circuit pattern electrically connected to a semiconductor element is provided on an insulating substrate on a cooler. A smoothing capacitor is disposed not to be overlapped with the semiconductor element in a plan view to include an inner electrode forming capacitance, a capacitor case housing the inner electrode, and a terminal protruding from the capacitor case seamlessly. A first sealing portion covers at least a part of each of the terminal of the smoothing capacitor, the insulating substrate, and the circuit pattern. The terminal of the smoothing capacitor and the circuit pattern are directly connected to each other by bonding force of an interface between the terminal and the circuit pattern.