SMOP Bridge Structure for Dense Memory and Low-Latency Interconnects
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Solution Overview
Problem
Challenges in semiconductor manufacturing include device form-factor expansion due to DRAM device scaling, signal integrity impairments from electrical coupling noises, and computing performance degradation from signal latency in memory-on-package architectures.
Innovation Solution
A stacked memory-on-package (SMOP) design with a bridge structure that includes conductive planes and a metal redistribution layer (RDL) for direct signal and power interconnects, allowing for miniaturization and reduced signal latency through a stacked device architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DRAM devices are scaled laterally to improve computing performance, then memory bandwidth density increases, but package real-estate expands and device form-factor increases
Solution Approach 1:
The patent transitions from lateral (2D) arrangement of DRAM devices to a stacked (3D) configuration where memory devices are positioned vertically above the package substrate. This dimensional change allows multiple DRAM devices to be integrated within the same package footprint, increasing memory bandwidth density without expanding package real-estate.
Solution Approach 2:
The patent implements a nested structure where DRAM devices are stacked vertically, with each memory device positioned above the previous one. This nesting approach allows multiple functional layers to occupy the same horizontal space, effectively increasing device density while maintaining a compact package form-factor.
2Productivity
If DRAM devices are scaled laterally to improve computing performance, then memory bandwidth density increases, but device reliability risks increase due to package warpage control challenges
Solution Approach 1:
By stacking DRAM devices vertically rather than arranging them laterally, the patent reduces the overall package footprint and minimizes stress distribution across the package substrate. This vertical configuration decreases the likelihood of warpage and improves device reliability while maintaining high memory bandwidth density.
3Area of stationary object
If transmission lines are tightly coupled between CPU/SOC/GPU and DRAM devices, then package substrate footprint is reduced, but signal integrity deteriorates due to electrical coupling noises
Solution Approach 1:
The patent utilizes vertical stacking to position DRAM devices above the package substrate, creating three-dimensional signal paths that reduce lateral coupling between transmission lines. This spatial separation in the vertical dimension maintains compact package footprint while minimizing electrical coupling noises and improving signal integrity.
4Quantity of substance
If package substrate footprint is expanded to house additional DRAM devices, then memory device capacity increases, but device miniaturization is inhibited
Solution Approach 1:
The patent achieves increased memory device capacity by stacking DRAM devices vertically in multiple layers. This approach allows high-capacity memory integration within a compact three-dimensional package, avoiding lateral expansion and enabling continued device miniaturization while increasing storage capacity.
Data Source
AI summary
A semiconductor package includes a package substrate, a base die including a first die surface coupled to the package substrate, and a second die surface opposite to the first die surface, and a first device including a first device surface coupled to the package substrate, and a second device surface opposite to the first device surface. The semiconductor package further includes a second device including a third device surface coupled to the second device surface, and a fourth device surface opposite to the third device surface, and a bridge including a first portion coupled to the package substrate, and a second portion coupled to the first portion, the fourth device surface and the second die surface.