SMP ASMP Mode Switching Hardware Controller
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Solution Overview
Problem
Existing multi-processing systems face challenges in efficiently switching between symmetric and asymmetric multiprocessing modes, leading to higher power consumption and complexity, especially in smaller devices where only a subset of processors is needed for handling unbalanced loads.
Innovation Solution
A multi-processing system with a voltage regulator circuit and a controller that dynamically switches between SMP and ASMP modes by adjusting clock signals and supply voltages for a subset of processors, minimizing software intervention and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hardware-based switching between SMP and ASMP modes is implemented, then switching speed is improved, but device complexity increases
Solution Approach 1:
The system segments the processor group into a first processor and a second processor, allowing independent control of the second processor's operating parameters. This segmentation enables selective mode switching for specific processors without requiring complex system-wide reconfiguration, thus improving switching speed while limiting complexity growth to manageable segments.
Solution Approach 2:
The system implements dynamic switching between SMP and ASMP modes through hardware-based control mechanisms that can rapidly adjust processor operating states. The controller dynamically modifies clock signals and voltage levels for the second processor, enabling fast transitions between symmetric and asymmetric processing modes without software intervention delays.
2Use of energy by moving object
If ASMP mode is used with different clock frequencies for processors, then power efficiency is improved, but latency increases when data is stored in lower clock frequency portions of L2 cache
Solution Approach 1:
The system applies different clock frequencies to different processors based on their specific workload requirements. The second processor can operate at a lower clock frequency when handling memory-intensive tasks, reducing its power consumption, while the first processor maintains higher frequency for compute-intensive tasks. This localized frequency adjustment optimizes overall system power efficiency without uniformly increasing latency.
3Device complexity
If SMP mode is used with all processors operating at the same clock frequency, then system simplicity is maintained, but power consumption increases due to unbalanced workloads
Solution Approach 1:
The system changes the operating parameters (clock frequency and voltage) of the second processor dynamically based on workload characteristics. When the second processor handles memory-intensive tasks, its clock frequency and voltage are reduced, lowering power consumption. This parameter adjustment is controlled through hardware mechanisms that maintain system simplicity while achieving power optimization.
4Adaptability or versatility
If a voltage regulator circuit is added to generate different supply voltages for processors, then power management flexibility is improved, but device complexity and cost increase
Solution Approach 1:
The voltage regulator circuit is designed to serve multiple functions: it generates different voltage levels for different processors, provides power management control, and supports both SMP and ASMP operating modes. This multi-functionality reduces the need for separate voltage regulation circuits for each processor, thereby limiting the increase in overall device complexity while maintaining power management flexibility.
Data Source
AI summary
A processing system includes multiple processors in which a first processor operates at a first clock frequency and first supply voltage at all times. At least one processor is dynamically switchable to operate at the first clock frequency and first supply voltage resulting in the first and second processors providing symmetrical multi-processing (SMP) or at a second clock frequency and a second supply voltage resulting in the first and second processors providing asymmetrical multi-processing (ASMP). An integrated controller (e.g., finite state-machine (FSM) controls not only voltage change, but also clock-switching. Various criteria can be used to determine when to switch the at least one switchable processor to improve power consumption and/or performance. Upon receipt of a switching command to switch between SMP and ASMP, a series or sequence of actions are performed to control a voltage supply and CPU/memory clock to the switchable processor and cache memory.