SMP Clocking Scheme Balancing Skew via Equal Path Lengths
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Solution Overview
Problem
Current small-scale multi-processor systems lack a synchronization clocking scheme to facilitate flexible symmetric multi-processing across different bootable domains, as they operate independently with unsynchronized clocks.
Innovation Solution
A clocking scheme that includes a clock source, Select Phase-Locked Loops (SPLLs), clock buffers, and a self-clock path with equal lengths to the distribution-clock path, allowing for synchronized clock distribution between SMP domains, with a select signal generated by glue logic to select the base clock and generate an N-times faster clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If independent clock sources are used for each SMP domain, then each domain can operate independently as a bootable domain, but the system lacks flexible SMP configuration across different domains
Solution Approach 1:
The clock source is designed to serve multiple functions: it can provide clocks to a single SMP domain for independent operation, or synchronize multiple SMP domains for flexible SMP configuration. The SPLL units are universally applicable across all domains, each capable of receiving and processing clock signals from any other domain, thus enabling both independent and synchronized operation modes without requiring different hardware configurations.
Solution Approach 2:
The SPLL acts as an intermediary device between the clock source and the processors. It receives clock signals from either the local clock source or remote SPLLs through distribution clock paths, processes these signals, and provides synchronized clocks to processors. This intermediary mechanism enables flexible SMP configuration by mediating clock distribution across domain boundaries while maintaining signal integrity and synchronization.
2Ease of operation
If clock paths of different lengths are used for self-clock and distribution-clock, then routing flexibility is improved, but clock skew and propagation delay increase
Solution Approach 1:
The system allows asymmetric clock path configurations where self-clock paths and distribution-clock paths can have different physical routes and lengths, providing routing flexibility. The asymmetry is compensated by the SPLL's ability to process and synchronize clocks from paths of varying lengths, enabling flexible PCB layout and routing while maintaining clock synchronization through the intelligent clock selection and distribution mechanism.
3Reliability
If multiple independent clock sources are used for each SMP domain, then domain independence is maintained, but system-wide clock synchronization cannot be achieved
Solution Approach 1:
The system dynamically switches between independent and synchronized operation modes. Each SMP domain can independently select its clock source through the SPLL, allowing the system to adapt its clocking architecture based on operational requirements. When domains need to operate independently, each uses its local clock source; when synchronized operation is required, domains can select clock signals from other domains, thus achieving both reliability through independence and adaptability through synchronization capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables flexible SMP configuration by synchronizing clocks across domains, balancing skew and propagation delay, and allowing for larger SMP configurations with reduced design complexity and independence from bootable SMP domain or CPU board design.
Implementation Method 1
The SPLL is for receiving the base clocks from each of the SMP domains, and for selecting one of the base clocks according to a select signal, and eventually generates an N-times faster clock
Data Source
AI summary
A clocking scheme is provided to synchronize system clock across plural independent SMP (Symmetric Multi-Processing) domains of the multi-processor system. Each of the SMP domains is connected with another through an interconnection board and two or more identical connectors. The clocking scheme includes a clock source, a SPLL (Select Phase-Locked Loop) and a clock buffer on each of the SMP domains to provide a dedicated base clock. A self-clock path is used to send the base clock from the clock source to the SPLL on the same SMP domain, and on the other hand one or more base clock is sent through a distribution-clock path to another SPLL. The distribution-clock path and the self-clock path will have equal lengths, making the base clock pass through the two connectors or the same connector twice to achieve the similar electrical characteristics and balance the skew or propagation delay.