SMP Core Architecture for Exascale Computing With Fixed Latency
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Solution Overview
Problem
Existing supercomputers face limitations in achieving exascale performance due to communication bottlenecks, unreliable memory access, and unpredictable latency in message processing, which hinder the ability to run algorithms like Block LU Decomposition at exaflop levels for extended periods.
Innovation Solution
The implementation of Simultaneous Multi-Processor (SMP) cores with advanced communication channels and error correction, combined with Anticipator Chips that anticipate memory access needs, and a new communication network that ensures fixed latency and fault resilience, along with optical fiber links for reduced complexity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional supercomputer architectures are used to achieve high computational performance, then processing speed improves, but communication bottlenecks and unpredictable latency worsen
Solution Approach 1:
The system is divided into multiple independent Simultaneous Multi-Processor (SMP) cores, each capable of autonomous operation. This segmentation allows computational tasks to be distributed across numerous cores while maintaining independent communication channels, thereby reducing communication bottlenecks and improving both speed and reliability.
Solution Approach 2:
Optical fiber links are introduced as an intermediary communication medium between SMP cores and memory systems. This intermediary provides fixed-latency, high-bandwidth communication that eliminates the unpredictable latency of traditional electrical interconnects, resolving the contradiction between high-speed computation and reliable communication.
2Productivity
If system complexity is increased to achieve exascale performance, then computational capability improves, but fault tolerance and reliability worsen
Solution Approach 1:
Error correction codes and fault detection mechanisms are built into the SMP core architecture and communication channels before faults occur. This beforehand cushioning allows the system to detect and correct errors automatically, maintaining reliability even as system complexity increases to achieve exascale performance.
Solution Approach 2:
The system changes the operational parameters of SMP cores dynamically, adjusting execution waves and resource allocation based on detected conditions. This allows the system to maintain optimal performance while adapting to faults, thereby preserving both productivity and reliability at exascale.
3Productivity
If memory access speed is increased to improve algorithm performance, then computational throughput improves, but access reliability and predictability worsen
Solution Approach 1:
The Anticipator Chip performs preliminary actions by predicting future memory access patterns and pre-fetching data before it is actually needed. This preliminary action eliminates unpredictable memory access latency while maintaining high computational throughput, as data is ready when needed without stalling the computation.
Solution Approach 2:
The system maintains continuous useful action through overlapping memory operations with computation. Multiple execution waves are pipelined such that while one wave accesses memory, another performs computation, eliminating idle time and ensuring continuous productive work without sacrificing reliability.
4Speed
If parallel processing is increased to achieve higher performance, then algorithm execution speed improves, but communication overhead and system complexity worsen
Solution Approach 1:
The optical fiber communication network is designed with universal interfaces and protocols that work across all SMP cores and memory systems. This multi-functionality allows the same communication infrastructure to support multiple parallel processing operations simultaneously, reducing overall system complexity while maintaining high execution speed.
Data Source
AI summary
Apparatus adapted for exascale computers are disclosed. The apparatus includes, but is not limited to at least one of: a system, data processor chip (DPC), Landing module (LM), chips including LM, anticipator chips, simultaneous multi-processor (SMP) cores, SMP channel (SMPC) cores, channels, bundles of channels, printed circuit boards (PCB) including bundles, floating point adders, accumulation managers, QUAD Link Anticipating Memory (QUADLAM), communication networks extended by coupling links of QUADLAM, log 2 calculators, exp2 calculators, log ALU, Non-Linear Accelerator (NLA), and stairways. Methods of algorithm and program development, verification and debugging are also disclosed. Collectively, embodiments of these elements disclose a class of supercomputers that obsolete Amdahl's Law, providing cabinets of petaflop performance and systems that may meet or exceed an exaflop of performance for Block LU Decomposition (Linpack).