SMP OS Thread Context Virtualization for Interrupt Scalability
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Solution Overview
Problem
Existing multiprocessor operating systems do not effectively utilize lightweight thread contexts in MIPS MT ASE processors, limiting their ability to appear as multiple CPUs to the operating system, which hinders scalability and efficient resource management.
Innovation Solution
Modifying SMP operating systems to enable lightweight thread contexts within a multithreaded processor to function as physical CPUs, allowing each thread context to control interrupt requests and share resources like TLBs and floating-point coprocessors, thereby enabling the operating system to schedule threads across multiple thread contexts as if they were separate processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If lightweight thread contexts are used in MIPS MT ASE processors, then resource utilization and scalability are improved, but the ability to appear as multiple independent CPUs to the operating system deteriorates
Solution Approach 1:
The patent creates virtual copies of CPU functionality at the thread context level. Each lightweight thread context is configured with its own program counter, register file, and exception handling capability, effectively copying essential CPU state components to enable the operating system to treat each thread context as an independent processor while maintaining resource sharing benefits
2Productivity
If thread contexts share resources like TLBs and floating-point coprocessors, then resource utilization is improved, but interrupt handling and exception domain management become more complex
Solution Approach 1:
The patent segments the exception domain into virtual processing elements (VPEs), where each VPE is assigned a specific subset of thread contexts. This segmentation allows interrupt requests to be routed to specific VPEs rather than requiring global interrupt management across all thread contexts, simplifying the complexity while maintaining resource sharing benefits
Solution Approach 2:
The patent introduces virtual processing elements (VPEs) as intermediary layers between the operating system and lightweight thread contexts. VPEs act as mediators that manage interrupt requests and exception domains, allowing thread contexts to share resources while maintaining clear interrupt handling boundaries through the VPE abstraction layer
3Productivity
If SMP operating systems are modified to treat thread contexts as physical CPUs, then scheduling efficiency is improved, but system complexity increases
Solution Approach 1:
The patent makes thread contexts universally compatible with standard SMP operating system interfaces by implementing full CPU-like functionality including program counters, register files, and exception handling. This universality allows existing SMP scheduling mechanisms to work directly with thread contexts without requiring fundamental changes to operating system architecture, improving scheduling efficiency while limiting complexity increases
Data Source
AI summary
A multiprocessing system is disclosed. The system includes a multithreading microprocessor, including a plurality of thread contexts (TCs), each comprising a first control indicator for controlling whether the TC is exempt from servicing interrupt requests to an exception domain for the plurality of TCs, and a virtual processing element (VPE), comprising the exception domain, configured to receive the interrupt requests, wherein the interrupt requests are non-specific to the plurality of TCs, wherein the VPE is configured to select a non-exempt one of the plurality of TCs to service each of the interrupt requests, the VPE further comprising a second control indicator for controlling whether the VPE is enabled to select one of the plurality of TCs to service the interrupt requests. The system also includes a multiprocessor operating system (OS), configured to initially set the second control indicator to enable the VPE to service the interrupts, and further configured to schedule execution of threads on the plurality of TCs, wherein each of the threads is configured to individually disable itself from servicing the interrupts by setting the first control indicator, rather than by clearing the second control indicator.