Multi-rate SMPS Controller Phase Delay Reduction
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Solution Overview
Problem
Conventional switched mode power supplies (SMPS) experience performance limitations due to phase loss caused by delays in duty cycle control signal calculation and propagation, leading to suboptimal load transient response and oscillations, which are exacerbated by filtering processes that introduce phase lag and distortion.
Innovation Solution
A multi-rate controller is employed that samples the output voltage at a frequency higher than the reference signal, filters out ripple components using an interpolated low-pass filter, and generates duty cycle control signals through a PID controller with scaled and down-sampled signals, reducing phase loss and distortion while effectively suppressing voltage ripple.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional Nyquist-sampled controller is used to generate duty cycle control signals, then device complexity is reduced, but phase loss increases leading to degraded load transient response
Solution Approach 1:
The patent applies preliminary action by calculating and storing predicted ripple values in advance for multiple future time points. The ripple predictor computes ripple values based on historical data and stores them in a buffer, so that when needed for compensation, the values are already available. This eliminates the need for real-time calculation during critical control moments, reducing phase delay while maintaining controller functionality.
2Stability of the object's composition
If filtering processes are applied to suppress voltage ripple, then output voltage stability is improved, but phase lag and distortion increase leading to oscillations
Solution Approach 1:
The patent applies the extraction principle by separating the ripple component from the output voltage signal using a ripple predictor. Instead of applying broad filtering that affects the entire signal, the system specifically extracts and compensates for the ripple component based on predicted values. This targeted approach suppresses voltage ripple while minimizing phase lag and distortion that would result from conventional filtering methods.
3Loss of time
If multi-rate controller with high-speed ADC and DSP is used to reduce phase loss, then load transient response is improved, but power consumption and silicon area increase
Solution Approach 1:
The patent applies parameter changes by modifying the control approach from high-speed real-time processing to a method that uses predicted values at lower effective rates. The system changes the operating parameters of the ADC and DSP by using them at reduced speeds with predictive compensation, rather than requiring full high-speed operation. This reduces power consumption and silicon area while maintaining the phase response benefits through the ripple prediction mechanism.
4Loss of time
If multi-rate controller with high-speed ADC and DSP is used to reduce phase loss, then load transient response is improved, but device complexity and cost increase
Solution Approach 1:
The patent reduces controller complexity by applying preliminary action through pre-calculation and storage of ripple prediction values. Instead of requiring complex high-speed processing circuitry, the system uses a buffer to store pre-computed values that can be retrieved and applied with simpler, lower-speed hardware. This maintains the phase response improvement while significantly reducing the complexity and cost of the controller implementation.
Data Source
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AI summary
There is provided controller arranged to generate a control signal, SD, for controlling an output voltage of a switched mode power supply, SMPS, the SMPS controlling its switching based on SD and an oscillatory reference signal SRef. The controller comprises: a sampling module (150) that samples a signal indicative of the output voltage of the SMPS at a frequency higher than a frequency of SRef; a filter module (160) that filters out a ripple component of the sampled signal to generate a filtered signal, SF; and a PID controller arranged to generate SD based on SF. The PID controller comprises : a first component that scales sample values of SF by a factor Kp to generate a first component signal; a down-sampling module (170-2) that generates a down- sampled signal, SDC, by sampling, at the frequency of SRej, a signal based on the sampled signal; a storage module (170-4) that stores a value of SDC; a second component that generates a second component signal by calculating values of a product of a factor Kd and a difference signal, the difference signal being the difference between each sample value in SF and the stored value. The PID controller is arranged such that each value of the difference signal represents the difference between a respective value of SF that is based on a respective one or more samples obtained by the sampling module (150) during a period of the reference signal, and a value of SDC that is based on a sample obtained by the sampling module (150 ) in a preceding period; a third component that scales SDC by a factor Ki and accumulates values of the scaled, down-sampled signal to generate a third component signal,- and a summing module that generates SD by summing the first, second and third component signals.