SMPS Snooze Mode Control for Low Quiescent Current
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Solution Overview
Problem
Switched mode power supplies (SMPS) face challenges in reducing quiescent current consumption, especially during light load conditions, which can deplete depletable power sources and increase energy consumption from non-depletable sources, leading to reduced lifespan and higher costs.
Innovation Solution
The implementation of a snooze mode in SMPS controllers that adjusts the clock signal frequency based on output voltage stability, using a combination of zero-crossing detection and fast drop detection signals to reduce monitoring and thus lower quiescent current draw, while maintaining regulated output voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If continuous monitoring of output voltage is performed to maintain regulated output voltage, then output voltage stability is improved, but quiescent current consumption increases
Solution Approach 1:
The patent implements a snooze mode that periodically suspends monitoring operations when the output voltage remains stable within regulation bounds. The controller alternates between active monitoring phases and suspended monitoring phases, reducing quiescent current consumption during light load conditions while maintaining output voltage stability through periodic checks.
2Speed
If monitoring frequency is increased to detect output voltage changes quickly, then response time to voltage changes is improved, but quiescent current consumption increases
Solution Approach 1:
The patent dynamically adjusts the monitoring frequency based on load conditions. During light load conditions, the controller enters snooze mode with reduced monitoring frequency to conserve energy. When load changes are detected or output voltage approaches regulation boundaries, the controller transitions to higher frequency monitoring to ensure rapid response to voltage changes.
Data Source
AI summary
A control signal generator includes an error amplifier, a first comparator, a second comparator, a logic circuit and a pulse generator. The error amplifier has a first output, a first input, a second input and a first snooze input. The first comparator has a second output, a third input and a fourth input. The third input is coupled to the first output. The second comparator has a third output, a fifth input, a sixth input and a second snooze input. The fifth input is coupled to the third input. The logic circuit has a fourth output and logic circuit inputs, including a first logic circuit input coupled to the second output. The pulse generator has a fifth output and a seventh input. The seventh input is coupled to the fourth output. A snooze mode controller has a sixth output coupled to the first snooze input and the second snooze input.