SMS4 Encryption Data Conversion Parallel Sub-Units
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Solution Overview
Problem
Conventional SMS4 cryptographic systems suffer from low encryption efficiency due to repeated data conversion processes, which are time-consuming and resource-intensive, leading to increased clock frequency requirements that complicate integrated circuit design and result in higher costs and interference issues.
Innovation Solution
The method involves optimizing the data conversion process by arranging constant arrays and employing multiple data converting sub-units, reducing the number of conversion cycles required to achieve the final result, thereby improving encryption efficiency and allowing for lower clock frequencies without compromising performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data conversion processing is repeated many times (32 times for 128-bit data), then encryption completeness is achieved, but encryption efficiency becomes low
Solution Approach 1:
The patent divides the data conversion process into parallel segments by introducing multiple data converting sub-units (first, second, third, and fourth data converting sub-units). Each sub-unit performs conversion operations on different data blocks simultaneously, reducing the total number of sequential conversion cycles from 32 to 8 clock periods while maintaining encryption completeness.
Solution Approach 2:
The patent transitions from a single-dimensional sequential conversion process to a multi-dimensional parallel process by organizing data converting sub-units in parallel across multiple clock periods. This dimensional change allows simultaneous execution of conversion operations on different data blocks, achieving both correctness and efficiency.
2Productivity
If clock frequency is increased to improve encryption efficiency, then encryption speed increases, but integrated circuit design becomes more difficult and costly
Solution Approach 1:
The patent segments the data conversion function into multiple independent sub-units that operate in parallel. This segmentation allows the system to achieve high encryption efficiency without increasing clock frequency, as the parallel structure naturally distributes the workload across multiple clock periods, thereby simplifying integrated circuit design.
Solution Approach 2:
The patent introduces dynamic control mechanisms through control signals (first control signal and second control signal) that coordinate the operation of multiple data converting sub-units. This dynamic control enables flexible parallel processing without requiring high clock frequencies, making the integrated circuit design more adaptable and less complex.
3Reliability
If data conversion processing is repeated many times, then encryption completeness is achieved, but signal interference increases and design cost increases
Solution Approach 1:
The patent segments the sequential conversion process into parallel operations across multiple sub-units. By distributing the conversion operations across different clock periods rather than repeating them sequentially, the patent reduces signal interference while maintaining encryption correctness through the coordinated parallel processing of multiple data blocks.
Data Source
AI summary
An encryption and decryption processing method, system and computer-accessible medium for achieving SMS4 cryptographic procedure/algorithm can be provided. First, constant arrays can prepared, the external data are input into a data registering unit and the first data conversion is addressed. Secondly, the second data conversion is addressed. Thirdly, the second data conversion is repeated until completing all the prescribed data conversion. Then, the results of repeating encryption and decryption processing are achieved.