Superscalar SMT Core Deterministic Mode via Dual-Issue Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Superscalar simultaneous multi-threaded (SMT) processors introduce indeterminism in real-time applications due to resource sharing between threads, making it challenging to meet precise execution deadlines and requiring improved deterministic execution modes.

Innovation Solution

A task-identifier-based mechanism temporarily disables the dual-issue capability of threads in an SMT core to ensure deterministic execution, allowing for predictable execution times by managing resource usage based on task requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If dual-issue capability is enabled in SMT core, then productivity is improved through parallel instruction execution, but determinism deteriorates due to resource sharing between threads

Engineering Contradiction:
Improveinstruction execution throughputVSAvoidexecution time determinism
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system dynamically adjusts the dual-issue capability based on task requirements. When a real-time task is detected, the dual-issue capability is temporarily disabled to ensure deterministic execution. When non-real-time tasks are detected, the dual-issue capability is enabled to maximize throughput. This dynamic switching resolves the contradiction by adapting the resource sharing behavior to the specific execution context.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the operational parameters of the SMT core by modifying the dual-issue enablement state. The parameter transitions between enabled and disabled states based on task classification, allowing the system to optimize for either productivity or determinism depending on the current workload requirements.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If multiple threads share processor resources, then productivity is improved through resource utilization, but execution time predictability worsens due to resource contention

Engineering Contradiction:
Improveprocessor resource utilizationVSAvoidexecution time variation
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The system segments the execution modes into distinct states: deterministic mode for real-time tasks and non-deterministic mode for non-real-time tasks. This segmentation allows each thread to execute with appropriate resource allocation guarantees, preventing resource contention from causing execution time variations in real-time tasks while still allowing resource sharing for non-real-time tasks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system introduces an intermediary mechanism (task identifier-based detection and control logic) that mediates resource access between threads. This intermediary monitors task characteristics and controls dual-issue enablement accordingly, acting as a gatekeeper that prevents resource contention when determinism is required while permitting resource sharing when productivity is prioritized.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If deterministic mode is enforced by disabling dual-issue, then execution time determinism is improved, but productivity decreases due to reduced parallel execution

Engineering Contradiction:
Improveexecution time determinismVSAvoidinstruction execution throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system applies periodic switching between deterministic and non-deterministic modes based on task arrival and completion. Rather than maintaining a fixed state, the dual-issue capability is periodically enabled or disabled according to the real-time task schedule, allowing the system to achieve determinism during critical periods while maintaining high productivity during non-critical periods.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS10572261B2Providing task-triggered deterministic operational mode for simultaneous multi-threaded superscalar processor
Publication Date: 2020.02.25 NXP USA INC
  • US10572261B2 patent drawing
  • US10572261B2 patent drawing
  • US10572261B2 patent drawing

AI summary

A task identifier-based mechanism is configured to temporarily disable a dual-issue capability of one or more threads in a superscalar simultaneous multi-threaded core. The core executes a first thread and a second thread which are each provided with a dual-issue capability wherein up to two instructions may be issued in parallel. In response to a task identifier being received that is indicative of a task requiring an improved level of determinism, the dual-issue capability of at least one of the first thread or the second thread is temporarily disabled.