Mitigating SMT Sensing Variations in Multi-State Flash Memory
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Solution Overview
Problem
The programming and reading performance of multi-state flash memory devices is significantly slowed due to the need for controlled programming procedures to achieve reasonable memory reliability, leading to increased programming pulses and verification steps, which decrease speed and efficiency.
Innovation Solution
Implementing simultaneous multi-threshold (SMT) sensing using different bias conditions to verify and read memory cells, allowing for faster programming by using two or more FSENSE times and applying different gate-to-source or drain-to-source voltages to verify multiple threshold voltages simultaneously, and compensating for cell-to-cell variations during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If controlled programming procedures with small programming steps and verification after each pulse are used to achieve narrow cell voltage distributions and reasonable memory reliability, then manufacturing precision and reliability are improved, but programming speed and productivity deteriorate
Solution Approach 1:
The memory array is divided into multiple sub-arrays, and different verify levels are applied to different sub-arrays simultaneously. This segmentation allows parallel verification of multiple threshold voltage levels, reducing the total number of sequential verify operations needed while maintaining narrow cell voltage distributions.
Solution Approach 2:
The patent introduces a spatial dimension to the verification process by applying different verify levels to different physical sub-arrays at the same time. This transforms the verification process from a single-dimensional sequential operation into a multi-dimensional parallel operation, significantly improving programming speed while maintaining reliability.
2Quantity of substance
If multiple distinct threshold voltage ranges are used to store multiple bits per cell, then storage capacity is improved, but the number of verification steps and programming pulses increases, causing programming speed to deteriorate
Solution Approach 1:
Multiple verification operations for different threshold voltage levels are merged into a single simultaneous verify operation. By applying different verify levels to different sub-arrays at the same time, the patent combines what would otherwise be sequential verification steps into one parallel operation, maintaining multi-bit storage capacity while improving programming speed.
Solution Approach 2:
The patent ensures continuous useful action by overlapping programming and verification operations across different sub-arrays. While one sub-array is being verified at a lower threshold level, another sub-array is simultaneously verified at a higher threshold level, eliminating idle time and maintaining continuous productive operation throughout the programming process.
3Productivity
If simultaneous multi-threshold sensing is used to verify multiple threshold voltages at the same time, then programming speed is improved, but cell-to-cell variations and sensing accuracy deteriorate
Solution Approach 1:
Different sub-arrays are assigned different verify levels appropriate to their specific programming requirements. Each sub-array receives a tailored verify level that matches its target threshold voltage range, ensuring high sensing accuracy for each local region while maintaining overall parallel operation across the entire memory array.
Data Source
AI summary
Methods and devices for mitigating sensing variations that may arise from simultaneous multi-threshold (SMT) sensing are provided. During SMT sensing, two or more different bias conditions may be used to simultaneously sense two different threshold voltages. However, there may be variances in the threshold voltage shift of memory cells when read with a different bias condition than was used to verify. In one embodiment each programmed state is read using both (or all) bias conditions that were used during SMT verify. In other words, two (or more) different sense operations are used to read each memory cell. The data from these different sense operations may be used to compute initialization values (e.g., LLRs, LRs, probabilities) for an ECC decoder. In one embodiment, this technique is only performed when a normal read fails.