SMU Interrupt Interception for CPU Power Reduction
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Solution Overview
Problem
Conventional computing systems consume excessive power due to CPU activity even during low or no activity levels, as interrupts from devices like mice or system updates require CPU processing, leading to increased power consumption.
Innovation Solution
A system and method that transitions a computing system between low and high power modes by using a System Management Unit (SMU) to intercept and process interrupts, storing critical operating states, and configuring the CPU to operate in low power mode, allowing the SMU to manage interrupts and resume CPU processing when activity increases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the CPU processes interrupts even during low activity periods, then system responsiveness is maintained, but power consumption increases
Solution Approach 1:
The patent extracts the interrupt processing function from the CPU and assigns it to a separate low-power interrupt controller. This allows the CPU to be powered down or placed in idle state while the interrupt controller continues to handle interrupts from input devices, display updates, and system clock, thereby maintaining system responsiveness while significantly reducing CPU power consumption during idle periods
Solution Approach 2:
The patent introduces an interrupt controller as an intermediary component between the input devices and the CPU. This intermediary component remains active in a low-power state to intercept and process interrupts, preventing them from waking up the CPU unnecessarily. The interrupt controller acts as a mediator that filters and manages interrupt traffic, allowing the CPU to remain in a low-power state while still responding to critical events
2Use of energy by moving object
If the CPU is kept powered off during idle time, then power consumption is reduced, but interrupt processing capability is lost
Solution Approach 1:
The patent segments the system into two functional parts: a always-on interrupt controller and an on-demand CPU. The interrupt controller is segmented as a separate low-power component that continuously monitors and processes interrupts, while the CPU is segmented as a high-power component that only activates when necessary. This segmentation allows interrupt processing capability to be maintained in the interrupt controller while the CPU remains powered off during idle periods
Solution Approach 2:
The patent implements preliminary action by having the interrupt controller pre-process interrupts before they reach the CPU. The interrupt controller is configured in advance to handle routine interrupts independently, so that when the CPU is powered off, these pre-configured interrupt handlers can still process incoming interrupts without requiring CPU activation. This preliminary setup ensures interrupt processing capability is maintained without keeping the full CPU powered on
Data Source
AI summary
A system and method for transitions a computing system between operating modes that have different power consumption characteristics. When a system management unit (SMU) determines that the computing system is in a low activity state, the SMU transitions the central processing unit (CPU) into a low power operating mode after the CPU stores critical operating state of the CPU in a memory. The SMU then intercepts and processes interrupts intended for the CPU, modifying a copy of the critical operating state. This effectively extends the time during which the CPU stays in lower power mode. When the SMU determines that the computing system exits a low activity state, the copy of the critical operating state is stored in the memory and the SMU transitions the CPU into a high power operating mode using the modified critical operating state.