Stacked Semiconductor Chip Junctions via Sn-Ag Alloy Reflow
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Solution Overview
Problem
The existing methods for manufacturing semiconductor devices with stacked semiconductor chips face challenges in forming strong junctions between through-hole electrodes, leading to potential issues with chip stacking and yield due to overhanging shapes and the need for high-temperature reflow processes.
Innovation Solution
A method involving the formation of Sn—Ag alloy films on projecting electrodes, followed by reflowing at moderate temperatures to form an Au—Sn alloy for eutectic bonding, which allows for strong junctions between through-hole electrodes without the need for high-temperature reflow on each electrode, thereby preventing chip dropping and improving manufacturing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If high-temperature reflow process is used to form strong junctions between through-hole electrodes, then junction strength is improved, but manufacturing complexity and energy consumption increase
Solution Approach 1:
The patent changes the temperature parameter of the reflow process from high-temperature to moderate-temperature range, while compensating by optimizing the alloy composition (Sn-Ag ratio) to achieve eutectic bonding at lower temperatures, thus reducing manufacturing complexity and energy consumption while maintaining junction strength
Solution Approach 2:
The patent uses composite alloy materials (Sn-Ag alloy) combining different metals with complementary properties - tin provides low melting point for eutectic bonding, while silver enhances strength and wetting characteristics, enabling strong junctions at moderate temperatures without high-process complexity
2Strength
If high-temperature reflow is applied to each electrode individually, then junction strength is improved, but processing time and energy consumption increase
Solution Approach 1:
The patent merges multiple individual electrode reflow operations into a single collective reflow process that processes all through-hole electrodes simultaneously at moderate temperature, reducing total processing time and energy consumption while achieving equivalent junction strength through eutectic bonding
3Ease of manufacture
If overhanging shapes are formed on projecting electrodes, then electrode formation is simplified, but chip stacking reliability deteriorates due to potential chip dropping
Solution Approach 1:
The patent changes the alloy composition parameter to Sn-Ag eutectic composition, which enables complete reflow and smoothing of the electrode surface at moderate temperatures, eliminating overhanging shapes that cause chip dropping while maintaining ease of manufacture through simplified single-step reflow processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of high-reliability semiconductor devices with strong junctions between through-hole electrodes, enhancing manufacturing efficiency and preventing chip dropping during processing, while allowing for lower-temperature reflow for temporary fixation followed by high-temperature complete fixation.
Implementation Method 1
reflowing at moderate temperatures to form an Au—Sn alloy for eutectic bonding
Implementation Method 2
reflowing at moderate temperatures to form an Au—Sn alloy
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming a first opening in a substrate to expose an interconnect structure, forming a seed film on the substrate, forming a first projecting electrode buried inside the first opening protruding outward from the substrate, forming a first metal film on the first projecting electrode, attaching a first supporting substrate to the substrate with a first adhesion layer, forming a second opening in the substrate to expose the interconnect structure, forming a second projecting electrode buried inside the second opening and protruding outward from the substrate, forming a second metal film on the second projecting electrode, attaching a second supporting substrate to the substrate with a second adhesion layer, removing the first supporting substrate, the first adhesion layer, and an exposed part of the seed film, removing the second supporting substrate and the second adhesion layer, and cutting the substrate into the plurality of chips.