Sn-Cu Preform with Intermetallics for SiC Encapsulation

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Solution Overview

Problem

Current semiconductor encapsulation methods, using either resin or Sn-based solder, fail to provide sufficient heat resistance and reliability for SiC semiconductor elements, especially under high-temperature and temperature-changing environments, limiting their performance and durability.

Innovation Solution

A preform for semiconductor encapsulation composed of Sn or Sn alloy and Cu or Cu alloy, with at least 2% by weight of intermetallic compounds like Cu3Sn and Cu6Sn5, which forms a sealing layer with elevated re-melting temperature and reduced surface tension, eliminating the need for flux and preventing void formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If resin encapsulant is used as sealing layer, then ease of manufacture is improved, but heat resistance deteriorates (degrades above 150°C)

Engineering Contradiction:
Improveease of manufactureVSAvoidheat resistance
Core Design Contradiction:
Ease of manufactureVSTemperature

Solution Approach 1:

The patent uses a composite material consisting of Sn-based solder as the base matrix and intermetallic compounds (such as Cu3Sn, Cu6Sn5, FeSn2, CoSn5, Ni3Sn4, or AlSn3) as dispersed phases. This composite structure combines the low melting point and ease of processing of Sn-based solder with the high heat resistance of intermetallic compounds, enabling the sealing layer to maintain both manufacturability and thermal stability above 150°C.

Inventive Principle:
Principle #40Composite materials

2Ease of manufacture

If Sn-based solder is used as metal encapsulant, then ease of manufacture is improved, but heat resistance deteriorates (melting temperature 200-230°C insufficient for power devices)

Engineering Contradiction:
Improveease of manufactureVSAvoidheat resistance
Core Design Contradiction:
Ease of manufactureVSTemperature

Solution Approach 1:

The patent uses a composite material consisting of Sn-based solder as the base matrix and intermetallic compounds (such as Cu3Sn, Cu6Sn5, FeSn2, CoSn5, Ni3Sn4, or AlSn3) as dispersed phases. This composite structure combines the low melting point and ease of processing of Sn-based solder with the high heat resistance of intermetallic compounds, enabling the sealing layer to maintain both manufacturability and thermal stability above 150°C.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent changes the physical and chemical parameters of the Sn-based solder by controlling the content of intermetallic compounds to be 0.1-10 wt% (preferably 0.5-5 wt%). This parameter adjustment modifies the melting characteristics and thermal stability of the sealing layer, enabling it to resist temperatures above 150°C while maintaining ease of manufacture.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If Sn-based solder is used as sealing layer, then ease of manufacture is improved, but reliability deteriorates (void formation after prolonged high-temperature operation)

Engineering Contradiction:
Improveease of manufactureVSAvoidreliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent uses a composite material consisting of Sn-based solder as the base matrix and intermetallic compounds (such as Cu3Sn, Cu6Sn5, FeSn2, CoSn5, Ni3Sn4, or AlSn3) as dispersed phases. This composite structure combines the low melting point and ease of processing of Sn-based solder with the high heat resistance of intermetallic compounds, enabling the sealing layer to maintain both manufacturability and thermal stability above 150°C.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent incorporates intermetallic compounds into the Sn-based solder before the sealing process. These intermetallic compounds act as preventive measures that cushion against the formation of voids during prolonged high-temperature operation, thereby maintaining reliability without compromising ease of manufacture.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

4Device complexity

If resin encapsulant is used as sealing layer, then device complexity is reduced, but heat resistance deteriorates (limits SiC semiconductor element performance)

Engineering Contradiction:
Improvedevice complexityVSAvoidheat resistance
Core Design Contradiction:
Device complexityVSTemperature

Solution Approach 1:

The patent uses a composite material consisting of Sn-based solder as the base matrix and intermetallic compounds (such as Cu3Sn, Cu6Sn5, FeSn2, CoSn5, Ni3Sn4, or AlSn3) as dispersed phases. This composite structure combines the low melting point and ease of processing of Sn-based solder with the high heat resistance of intermetallic compounds, enabling the sealing layer to maintain both manufacturability and thermal stability above 150°C.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The preform achieves high heat resistance and reliability by forming a robust sealing layer at lower temperatures, preventing damage to semiconductor elements and enhancing the durability and performance of SiC semiconductor devices.

Implementation Method 1

a preform for semiconductor encapsulation which mainly includes a metal or alloy, the metal or alloy further includes Sn or Sn alloy, and, Cu or Cu alloy, and still further includes at least 2% by weight of an intermetallic compound of Cu and Sn

Methodology Applied
Scientific EffectIntermetallic compound formation: Chemical Bonding

Implementation Method 2

forms a sealing layer with elevated re-melting temperature and reduced surface tension, eliminating the need for flux and preventing void formation

Methodology Applied
Scientific EffectSurface tension reduction: Surface Tension

Data Source

PatentUS10629506B2Preform for semiconductor encapsulation
Publication Date: 2020.04.21 NAPRA
  • US10629506B2 patent drawing
  • US10629506B2 patent drawing

AI summary

Disclosed is a preform for semiconductor encapsulation, mainly containing a metal or alloy, the metal or alloy further containing Sn or Sn alloy, and, Cu or Cu alloy, and still further containing at least 2% by weight of an intermetallic compound of Cu and Sn.