Snap-to Pattern Validation for Semiconductor Design
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Solution Overview
Problem
Current semiconductor integrated circuit design tools face challenges in verifying manufacturability of numerous patterns due to illegal combinations of polygons, which are not explicitly prohibited, leading to inefficiencies in pattern validation.
Innovation Solution
The implementation of a 'snap-to' capability within the Templatyzer tool, which uses a golden library of cells to identify and modify invalid patterns into valid ones by determining approximate valid sizes and positions, thereby reducing the need for extensive manufacturability verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If individual polygon placement is used for custom cell design, then design flexibility is improved, but the number of patterns requiring verification increases
Solution Approach 1:
The patent segments the cell design into reusable pattern templates (golden patterns) that can be individually verified and then automatically assembled. Each template represents a validated building block, reducing the combinatorial explosion of verification scenarios while maintaining design flexibility through template selection and parameterization.
Solution Approach 2:
The patent performs preliminary verification by pre-validating golden patterns and their manufacturability before actual cell design. This advance verification establishes a library of approved patterns that can be freely combined without requiring re-verification, resolving the contradiction between design flexibility and verification complexity.
2Manufacturing precision
If extensive manufacturability verification is performed on all patterns, then manufacturing precision is improved, but productivity deteriorates
Solution Approach 1:
The system performs manufacturability verification in advance on a small set of golden patterns, storing the validation results for reuse. This preliminary action ensures high manufacturing precision for all derived patterns without repeating the verification process, thereby maintaining productivity.
Solution Approach 2:
The patent uses copying by referencing validated golden patterns multiple times in different cell designs. Once a pattern is verified, it can be copied and reused indefinitely without re-verification, ensuring consistent manufacturing precision while dramatically improving productivity through elimination of redundant verification steps.
3Device complexity
If a small set of golden patterns is used to represent valid patterns, then the verification process is simplified, but the adaptability of pattern design is reduced
Solution Approach 1:
The patent maintains adaptability by allowing parameterization of golden patterns (such as dimensions, positions, and orientations) while keeping the core pattern structure validated. This enables continuous variation within validated parameter ranges, simplifying verification while preserving design flexibility through parameter adjustment rather than structural changes.
Solution Approach 2:
The golden patterns serve multiple functions: they are both the verification reference and the building blocks for diverse cell designs. By designing golden patterns with universal applicability and parameterization capabilities, the system achieves both verification simplification and design adaptability through a single unified approach.
Data Source
AI summary
Described is a method for implementing a snap to capability that enables the manufactured of a valid pattern in a semiconductor device, based upon an originally invalid pattern.