Snapback ESD Protection Circuit with RC Trigger and Mirror Transistor
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Solution Overview
Problem
Conventional ESD protection circuits in electronic devices face challenges in providing stable trigger voltages while preventing latchup, especially when using snapback devices, which can lead to persistent current flow after an ESD event, affecting battery life and leakage issues.
Innovation Solution
A circuit structure incorporating a resistor-capacitor (RC) circuit with a trigger transistor, a mirror transistor, and a snapback device, where the mirror transistor transmits a reduced current to the snapback device's gate, allowing controlled current flow only during ESD events, thereby avoiding latchup and optimizing current requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large FET is used as an ESD discharge element, then ESD protection capability is improved, but leakage current increases and battery life decreases
Solution Approach 1:
The patent changes the operating parameters of the ESD protection circuit by using a snapback device that operates in a high-impedance state during normal operation (low leakage) and transitions to a low-impedance state during ESD events (high protection capability). The trigger voltage parameter is carefully controlled to ensure stable activation only during ESD events.
2Loss of energy
If a snapback device is used to reduce leakage, then leakage current is reduced, but latchup may occur causing persistent current flow
Solution Approach 1:
The patent introduces an intermediary RC circuit with a trigger transistor that mediates between the input signal and the snapback device. The RC circuit filters out noise and transient signals, while the trigger transistor provides controlled activation of the snapback device only when a genuine ESD event is detected, preventing false latchup.
Solution Approach 2:
The patent employs feedback mechanisms where the trigger transistor's gate is controlled by the RC circuit that monitors the voltage across the snapback device. This feedback ensures that the snapback device is activated only when the voltage exceeds the stable trigger threshold, and prevents spurious latchup by requiring sustained overvoltage conditions.
3Speed
If the trigger voltage is lowered to activate ESD protection earlier, then ESD response time is improved, but false triggering increases
Solution Approach 1:
The patent prepares the ESD protection circuit in advance by pre-charging the capacitor in the RC circuit and biasing the trigger transistor. When an ESD event occurs, the pre-prepared circuit can respond immediately without requiring additional activation time, achieving fast response while maintaining high trigger voltage to prevent false triggering.
Data Source
AI summary
Embodiments of the disclosure provide a circuit structure and method to control electrostatic discharge (ESD) events in a resistor-capacitor (RC) circuit. Circuit structures according to the disclosure may include a trigger transistor coupled in parallel with the RC circuit, and a gate terminal coupled to part of the RC circuit. A mirror transistor coupled in parallel with the RC circuit transmits a current that is less than a current through the trigger transistor. A snapback device has a gate terminal coupled to a source or drain of the mirror transistor, and a pair of anode/cathode terminals coupled in parallel with the RC circuit. A current at the gate terminal of the snapback device, derived from current in the mirror transistor, controls an anode/cathode current flow in the snapback device.