Multi-core Interconnection Bus with Snoop Caching Module
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Solution Overview
Problem
Modern multi-core processors face long access latency and performance loss due to the sequential access to local caches and shared caches, leading to inefficient inter-core communication and storage space wastage from repeated storage of address and data validity information.
Innovation Solution
A multi-core interconnection bus with a snoop and caching module that uses a two-stage returning mechanism to determine valid data locations, allowing parallel access to local and shared caches, and avoids repeated storage by storing cache data validity information and shared cache data only once.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the local cache is accessed first and then the shared cache is accessed, then the cache hierarchy is maintained, but the access latency increases and performance is lost
Solution Approach 1:
The snoop and caching module performs preliminary action by determining cache data validity information and identifying valid data locations in advance. When a data request arrives, the system has already prepared the validity information and can immediately redirect the request to the correct cache location, eliminating the sequential waiting time between local and shared cache accesses.
Solution Approach 2:
The invention adds a new dimension to the cache access mechanism by introducing a snoop and caching module that maintains validity information about multiple caches simultaneously. This module creates an additional lookup dimension that allows the system to determine data location without following the traditional sequential path, effectively adding a parallel decision-making layer to the cache hierarchy.
2Adaptability or versatility
If address and data validity information are stored repeatedly in multiple caches, then data accessibility is improved, but storage space is wasted
Solution Approach 1:
The invention extracts the validity information storage function from the traditional cache structure and places it in a separate snoop and caching module. This module specifically stores address arrays and cache data validity information, separating the metadata management from the actual data storage, thereby reducing redundant storage in each cache while maintaining accessibility.
Solution Approach 2:
The snoop and caching module acts as an intermediary between multiple caches and the processor cores. It maintains a centralized record of data validity information and uses this information to mediate access requests, directing them to the appropriate cache without requiring each cache to independently store and manage validity information about all other caches.
Data Source
AI summary
The present invention discloses a multi-core interconnection bus, including a request transceiver module adapted to receive a data request from a processor core, and forward the data request to a snoop and caching module through a request execution module, where the data request includes a request address; the snoop and caching module adapted to look up cache data validity information of the request address, acquire data from a shared cache, and sequentially return the cache data validity information and the data acquired from the shared cache to the request execution module; and the request execution module adapted to determine, based on the cache data validity information, a target processor core whose local cache stores valid data, forward the data request to the target processor core, and receive returned data; and determine response data from the data returned by the target processor core and that returned by the snoop and caching module, and return, through the request transceiver module, the response data to the processor core that initiates the data request. The present invention also discloses a corresponding inter-core communication method and a multi-core processor.