Snoop Control Circuits for Lock-Step Semiconductor Devices
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Solution Overview
Problem
Existing semiconductor devices face performance deterioration when switching to a dual-core lock-step mode required for high functional safety levels, such as ASIL D, due to the need for core synchronization, which results in process stop periods and decreased performance.
Innovation Solution
A semiconductor device configuration that includes two processors with separate caches and snoop control circuits, allowing for asynchronous execution and comparison of software lock-step results without synchronizing core inputs, using a controller to manage snoop operations and prevent unnecessary snoop operations that could spread faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual-core lock-step mode is implemented for high functional safety levels, then fault detection capability is improved, but process stop period increases and performance deteriorates
Solution Approach 1:
The patent segments the memory into three distinct areas: a first area for storing first execution results, a second area for storing second execution results, and a third area for other data. This segmentation allows independent access and comparison of execution results without requiring core synchronization, thereby maintaining fault detection capability while avoiding performance deterioration.
Solution Approach 2:
The patent introduces snoop control circuits as intermediaries between the processors and memory. These circuits control snoop operations to prevent unnecessary memory access and fault propagation, enabling the system to maintain high functional safety levels without the performance penalty of full core synchronization.
2Reliability
If core synchronization is performed when switching to dual-core lock-step mode, then functional safety level is improved, but process stop period increases
Solution Approach 1:
The patent implements preliminary action by pre-configuring the memory with segmented areas and establishing snoop control circuits before lock-step operation begins. This preparation allows the system to switch to lock-step mode without requiring time-consuming core synchronization, as the infrastructure for independent operation is already in place.
Solution Approach 2:
The patent enables dynamic operation where the two cores can execute independently without synchronization while still maintaining functional safety through the snoop control mechanism. This dynamic approach eliminates the static requirement for core synchronization, thereby reducing process stop periods while maintaining safety levels.
3Stability of the object's composition
If snoop operations are permitted between processors, then cache coherence is improved, but fault propagation risk increases
Solution Approach 1:
The patent applies local quality by implementing selective snoop control where the snoop control circuits permit or prohibit snoop operations based on specific conditions and memory areas. This localized control maintains cache coherence where needed while preventing fault propagation in critical areas, thereby resolving the contradiction between coherence and fault isolation.
Data Source
AI summary
A semiconductor device includes first and second CPUs, first and second SPUs for controlling a snoop operation, a controller supporting ASIL D of a functional safety standard and a memory. The controller sets permission of the snoop operation to the first and second SPUs when a software lock-step is not performed. The controller sets prohibition of the snoop operation to the first and second SPUs when the software lock-step is performed. The first CPU executes a first software for the software lock-step, and writes an execution result in a first area for the memory. The second CPU executes a second software for the software lock-step, and writes an execution result in a second area of the memory. The execution result written in the first area is compared with the execution result written in the second area.