Snoop Control Unit for Cache Coherency in Dormant Processors
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Solution Overview
Problem
In multi-processing systems, maintaining cache coherency while allowing processors to enter a dormant power state is complicated, leading to potential repeated power state switches and diminished power saving benefits due to the need for immediate activation to service cache coherency actions.
Innovation Solution
A snoop control unit is configured to store markers indicating which local copies of data items need to be invalidated, allowing processors to remain in a dormant state until necessary, thus avoiding immediate activation and maintaining coherency without losing power-saving benefits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a processor enters a dormant power state to save power, then power consumption is reduced, but cache coherency cannot be maintained because the processor cannot respond to coherency operations
Solution Approach 1:
The snoop control unit stores markers in advance indicating which local cache copies need to be invalidated, so that when the processor wakes from dormant state, the invalidation actions are already prepared and can be executed immediately without requiring the processor to wake up for each coherency event
Solution Approach 2:
The snoop control unit acts as an intermediary between the memory system and the dormant processor, buffering coherency information in the form of markers so that the dormant processor does not need to be actively involved in real-time coherency operations
2Reliability
If a processor is immediately activated to service cache coherency operations, then cache coherency is maintained, but power saving benefits are lost due to repeated power state switches
Solution Approach 1:
Coherency markers are recorded in advance during the dormant period, allowing the processor to remain dormant and only wake up when necessary, thus avoiding repeated power state transitions while still maintaining coherency
3Speed
If local caches are used to improve access speed, then data access speed is improved, but cache coherency complexity increases due to the need to maintain consistency across multiple processors
Solution Approach 1:
The snoop control unit extracts and buffers coherency information in the form of markers, separating the coherency tracking function from the main processor logic and simplifying the overall system architecture
Solution Approach 2:
The snoop control unit maintains copies of coherency information in the form of markers, allowing the system to track cache validity states without requiring complex real-time communication between processors
Data Source
AI summary
A data processing apparatus and method has a plurality of processing units, at least one of which is configured to be switchable between an active power state and a dormant power state and the units share a memory, and at least one local storage unit is configured to store a local copy of a data item stored in the memory for access by an associated processing unit. A snoop control unit is monitors memory access requests and when one is issued, if the control unit has an indication that a local storage unit belonging to another dormant processing unit has a local copy of that data storage item and a cache coherency protocol required that the local copy of the requested data item associated with the other processing unit be invalidated, the control unit stores a marker indicating that that other local copy should later be invalidated.