Snoop Controller Multiprocessor Activation

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Solution Overview

Problem

Existing multiprocessor systems are inefficient in activating the second processor quickly, as they require sequential transmission of program data after initialization of inter-processor interfaces, leading to delayed activation.

Innovation Solution

Incorporating a snoop controller connected to both the read-only memory and random access memory, which determines and prioritizes program data transmission, allowing simultaneous initialization and data transfer, thereby enabling earlier activation of the second processor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If program data is transmitted sequentially after initialization of inter-processor interfaces, then transmission reliability is ensured, but activation time of the second processor increases

Engineering Contradiction:
Improvetransmission reliabilityVSAvoidactivation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The snoop controller performs preliminary actions by monitoring the bus during the initialization phase and pre-fetching program data for the second processor into an internal buffer before the actual activation occurs. This allows the program data to be ready immediately when the second processor needs to start executing, eliminating the sequential waiting time while maintaining transmission reliability through the buffered data transfer mechanism.

Inventive Principle:
Principle #10Preliminary action

2Speed

If program data transmission is prioritized and parallelized, then activation speed improves, but system complexity increases

Engineering Contradiction:
Improveactivation speedVSAvoidsystem complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The snoop controller acts as an intermediary component between the bus system and the second processor's memory. It monitors bus transactions during initialization, identifies program data transfers, and automatically captures this data into its internal buffer. This intermediary mechanism enables parallel data capture without requiring complex modifications to the existing processor architecture or memory subsystem, achieving speed improvement with minimal added complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of time

If the snoop controller monitors and captures program data during initialization, then data transfer time is reduced, but control complexity increases

Engineering Contradiction:
Improvedata transfer timeVSAvoidcontrol complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The snoop controller implements self-service functionality by autonomously monitoring bus transactions, identifying program data transfers to the second processor, and capturing this data into its buffer without requiring external control signals or complex coordination with other system components. The controller independently determines when to capture data based on its internal logic, simplifying the overall control architecture while achieving rapid data transfer during the initialization phase.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10909065B2Multiprocessor system
Publication Date: 2021.02.02 FUJIFILM BUSINESS INNOVATION CORP
  • US10909065B2 patent drawing
  • US10909065B2 patent drawing
  • US10909065B2 patent drawing

AI summary

A multiprocessor system including at least a first processor and a second processor, includes a storage unit that stores a first program executed by the first processor and a second program executed by the second processor, a memory unit that has a memory region used by the second processor, and a monitoring unit that is connected to the storage unit and the memory unit via a communication line, and, in a case where a program read from the storage unit is the second program, stores the read second program into the memory unit.