Credit-Aware Arbitration for Multi-Core Shared Memory Coherency
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Solution Overview
Problem
Multi-core systems face coherency issues due to simultaneous access to shared memory, leading to operational inefficiencies and potential outdated data retrieval, especially when software cache maintenance operations are slow or resource-intensive.
Innovation Solution
A multi-core shared memory controller (MSMC) with a snoop filter bank, cache tag bank, and memory bank is implemented, which includes coherent slave interfaces, an external memory master interface, and an arbiter circuit to manage memory access requests and determine snoop requests based on cache hit status and snoop filter states, ensuring coherent data access across processor packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software cache maintenance operations are used to manage coherency, then coherency can be maintained, but operational efficiency deteriorates due to slow performance and excessive operational time consumption
Solution Approach 1:
The patent replaces software-based cache maintenance operations with a hardware-based coherency management system. The snoop filter bank and cache tag bank operate in hardware to automatically detect and manage cache coherency states, eliminating the performance overhead of software intervention while maintaining coherency reliability across multi-core systems.
Solution Approach 2:
The patent introduces a snoop filter bank as an intermediary component between the cache tag bank and memory banks. This intermediary structure efficiently filters and manages coherency information, enabling rapid detection of cache states without requiring full software cache maintenance operations, thus improving operational efficiency while preserving coherency.
2Adaptability or versatility
If multiple processing cores access the same memory address simultaneously, then system functionality is enhanced, but coherency issues arise leading to outdated data retrieval
Solution Approach 1:
The patent implements a feedback mechanism where the snoop filter bank continuously monitors cache access states and provides real-time coherency information to the cache tag bank. This feedback loop enables the system to detect and resolve coherency issues dynamically, ensuring that all cores access up-to-date data while maintaining simultaneous multi-core access capability.
Solution Approach 2:
The patent performs preliminary coherency checking through the snoop filter bank before actual cache access occurs. By pre-establishing coherency states and filtering potential conflicts in advance, the system prevents outdated data retrieval while allowing multiple cores to access memory addresses simultaneously, thus maintaining both versatility and reliability.
3Productivity
If a hardware-based coherency management system is implemented, then operational efficiency is improved, but device complexity increases
Solution Approach 1:
The patent segments the coherency management function into distinct modular components: a snoop filter bank for filtering and monitoring, and cache tag banks for storing coherency information. This segmentation allows each component to perform its specific function efficiently, improving operational performance while organizing the complexity into manageable, independent modules that can be implemented systematically.
Data Source
AI summary
A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to determine a first destination device connected to the data path and associated with the first memory access request and a first credit threshold corresponding to the first memory access request. The arbiter circuit is further configured to determine a second destination device connected to the data path and associated with the second memory access request and a second credit threshold corresponding to the second memory access request. The arbiter circuit is configured to arbitrate access to the data path by the first memory access request and the second memory access request based on the first credit threshold and the second credit threshold.