Snoop Filter Cache-Line Migration Before Shared Memory Invalidation
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Solution Overview
Problem
In hierarchical memory systems, invalidating a cache line from a shared memory device leads to excessive read latency due to slower communication speeds between processors and shared memory devices, which can be mitigated by migrating data to dedicated memory devices.
Innovation Solution
A shared memory device with a snoop filter circuit and migration management circuit determines the hotness of cache lines based on access counts and triggers data migration to dedicated memory devices before cache line invalidation, using a back snoop circuit to refine this determination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored in shared memory device, then memory system cost is reduced, but read latency increases when cache line is invalidated
Solution Approach 1:
The system performs preliminary actions by monitoring cache line access patterns and proactively migrating frequently accessed data from shared memory to dedicated memory before cache invalidation occurs. The migration management circuit detects hot cache lines and triggers data migration in advance, ensuring that when cache lines are invalidated, the data is already positioned in faster dedicated memory, thus reducing read latency while maintaining cost benefits of shared memory architecture
Solution Approach 2:
The system implements feedback mechanisms through the migration management circuit that continuously monitors cache line access patterns and entry access counts. This feedback loop identifies hot cache lines and triggers automated data migration decisions, dynamically adjusting data placement between shared and dedicated memory based on actual access behavior, thereby optimizing the trade-off between cost and performance
2Loss of time
If data is migrated to dedicated memory device, then read latency is reduced, but memory system complexity increases
Solution Approach 1:
The system employs self-service mechanisms where the migration management circuit autonomously monitors cache line access patterns, determines hotness based on entry access counts, and automatically triggers data migration without external intervention. The back snoop circuit independently tracks invalidation events and coordinates with the migration management circuit, enabling the memory system to self-optimize data placement based on observed access behavior, thereby reducing read latency while managing complexity through automation
Solution Approach 2:
The migration management circuit acts as an intermediary between the cache system and memory subsystems. It receives information about cache line access patterns and invalidation events from the back snoop circuit, processes this information to determine migration needs, and coordinates data movement between shared and dedicated memory. This intermediary layer abstracts the complexity of data management, allowing the system to achieve optimized read latency without requiring complex direct coordination between all system components
3Measurement precision
If cache line access pattern is monitored, then data migration accuracy is improved, but circuit complexity increases
Solution Approach 1:
The system extracts only the essential information needed for migration decisions by monitoring entry access counts in the snoop filter circuit and invalidation events through the back snoop circuit. Rather than analyzing complete cache access patterns, the system focuses on extracting key metrics (access frequency and invalidation status) that directly indicate hot cache lines, thereby improving migration accuracy while minimizing the complexity of monitoring circuitry
Solution Approach 2:
The system utilizes parameter changes in the form of entry access counts that automatically update as cache lines are accessed. By monitoring changes in these count parameters and comparing them against thresholds, the migration management circuit can accurately identify hot cache lines without complex analysis. The parameter-based approach transforms complex access pattern recognition into simple threshold comparisons, improving migration accuracy while keeping circuit complexity manageable
Data Source
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AI summary
A shared memory device (100) includes a memory bank (BNK) that stores first raw data corresponding to a first cache line stored in a first processor (11) among processors (11, 12), a snoop filter circuit (110) including a first snoop filter entry (SFE) corresponding to the first cache line and a first entry access count (EAC) corresponding to the first snoop filter entry (SFE), and a migration management circuit (120) that determines a hotness of the first cache line based on the first entry access count (EAC) and issues a migration request for the first raw data to the first processor (11) based on the hotness.