Low Intrusion Snoop Invalidation for Multiprocessor Cache Coherency
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Solution Overview
Problem
In multiprocessor systems, cache coherency protocols like snooping increase complexity and power consumption due to frequent cache access and invalidation operations, especially as the number of processors sharing memory increases, leading to reduced performance and bandwidth.
Innovation Solution
Implementing a method and apparatus for low intrusion snoop invalidation by using separate invalidate bits to track potential cache entry invalidations, allowing for efficient coherency management without interfering with normal cache access operations, and clearing these bits after valid bits are invalidated.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If snooping is used to maintain cache coherency, then cache coherency is maintained, but cache access bandwidth is reduced and performance decreases
Solution Approach 1:
The patent segments the cache state tracking by introducing separate invalidate bits that are independent from the main cache valid bits. This segmentation allows the cache system to track potential invalidations without requiring full cache access operations, thereby maintaining coherency while preserving bandwidth.
Solution Approach 2:
The invalidate bits act as an intermediary mechanism between the snoop operation and the cache valid bits. Instead of directly accessing and invalidating cache entries on every snoop, the system uses these intermediary bits to track potential invalidations, reducing the intrusion into normal cache operations.
2Reliability
If snooping activity increases to maintain coherency in multiprocessor systems, then cache coherency is maintained, but power consumption increases
Solution Approach 1:
The patent applies partial action by using invalidate bits to track only the potential invalidation state without performing full cache access operations. This partial tracking mechanism reduces the energy required compared to complete cache invalidation procedures while still maintaining coherency.
Solution Approach 2:
The patent extracts the coherency tracking function from the main cache access path by implementing separate invalidate bits. This extraction allows the system to monitor and manage cache invalidations independently, reducing the power consumption associated with frequent full cache access operations.
3Productivity
If separate invalidate bits are used to track potential invalidations, then cache access bandwidth is preserved, but device complexity increases
Solution Approach 1:
The patent merges the invalidate bit array with the existing cache structure in a way that leverages available resources. By integrating the tracking mechanism into the existing cache framework rather than creating a completely separate system, the complexity increase is minimized while still achieving bandwidth preservation.
Data Source
AI summary
Efficient techniques are described for tracking a potential invalidation of a data cache entry in a data cache for which coherency is required. Coherency information is received that indicates a potential invalidation of a data cache entry. The coherency information in association with the data cache entry is retained to track the potential invalidation to the data cache entry. The retained coherency information is kept separate from state bits that are utilized in cache access operations. An invalidate bit, associated with a data cache entry, may be utilized to represents a potential invalidation of the data cache entry. The invalidate bit is set in response to the coherency information, to track the potential invalidation of the data cache entry. A valid bit associated with the data cache entry is set in response to the active invalidate bit and a memory synchronization command. The set invalidate bit is cleared after the valid bit has been cleared.