Snooper Cache Prefetching for Bandwidth Reduction

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Solution Overview

Problem

Current cache coherency protocols in multiprocessor systems are inefficient as they consume unnecessary bandwidth through system-wide broadcasts of updated cache lines, failing to guarantee timely visibility of cache line updates to all interested caches, leading to latency penalties.

Innovation Solution

Implementing an enhanced hover state with active prefetches, where a snooper issues a prefetch request for a modified cache line only to caches that held a prior copy, using a system-wide update complete operation to trigger the request and updating the cache memory with the new copy, while incrementing retries for failed requests.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If system-wide broadcast of updated cache line is used, then all caches are guaranteed to see the updated cache line, but unnecessary bandwidth is consumed on the interconnect

Engineering Contradiction:
Improvecache line update visibilityVSAvoidbandwidth consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies local quality by transitioning from a uniform system-wide broadcast approach to a selective, localized update mechanism. The snooper identifies specific caches that held the updated cache line and sends targeted prefetch requests only to those caches, rather than broadcasting to all caches in the system. This localized approach reduces interconnect bandwidth consumption while ensuring that only the necessary caches receive the updated data.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements preliminary action by having the snooper proactively issue prefetch requests to caches that previously held the cache line before those caches actually need the updated data. This anticipatory approach ensures that when the caches need the updated cache line, the data is already being transferred or has been transferred, reducing latency penalties while avoiding unnecessary broadcasts to caches that don't need the update.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If cache line update is propagated to all caches, then coherence is maintained, but latency penalties occur due to bandwidth consumption

Engineering Contradiction:
Improvecache coherenceVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent changes the parameter of update propagation from a blanket system-wide approach to a selective targeted approach. By modifying how updates are propagated—specifically, by having the snooper track which caches held the cache line and sending prefetch requests only to those caches—the system maintains cache coherence while reducing the time and bandwidth required for propagation.

Inventive Principle:
Principle #35Parameter changes

3Loss of energy

If no system-wide broadcast is used, then bandwidth is saved, but there is no guarantee that caches will see the updated cache line in time

Engineering Contradiction:
Improvebandwidth consumptionVSAvoidcache line update visibility
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The patent implements feedback by having the snooper track which caches previously held the cache line and use this information to determine where to send prefetch requests. This feedback mechanism ensures that updated cache lines are propagated to the correct caches that need them, maintaining reliability of update visibility while avoiding unnecessary broadcasts to caches that don't require the update.

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP2122470B1System and method for implementing an enhanced hover state with active prefetches
Publication Date: 2011.03.16 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • EP2122470B1 patent drawingFigure 1
  • EP2122470B1 patent drawingFigure 2
  • EP2122470B1 patent drawingFigure 3

AI summary

A system and method for implementing an enhanced hover state with active prefetches. According to a preferred embodiment of the present invention, a snooper in a processing unit receives a system-wide update complete operation indicating a completion of a storage-modifying operation targeting a particular address, where the storage-modifying operation results in a modified first cache line in a first cache memory. The snooper determines if a second cache memory held a second cache line associated with the particular address prior to receiving the system-wide update complete operation. If so, the snooper issues a prefetch request for a copy of the modified first cache line to replace the second cache line in the second cache memory. The snooper updates the second cache memory with a copy of the modified first cache line.