Snubber Circuit Withstand Voltage Detection in Semiconductor Devices

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Solution Overview

Problem

Existing semiconductor devices with snubber circuits lack a method to confirm the withstand voltage after integration, as the snubber circuit's potential is not distinguishable from the P and N electrodes, leading to undetectable cracks and reduced quality control.

Innovation Solution

A semiconductor device design where the snubber circuit is separated from the circuit pattern on an insulating substrate, with a resistance and capacitor positioned on distinct substrates, allowing for independent electrical connections and enabling the detection of withstand voltage through dielectric voltage-withstand tests.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the snubber circuit is integrated on the same conductive pattern as P and N electrodes, then the device complexity is reduced, but the measurement precision of withstand voltage cannot be confirmed

Engineering Contradiction:
Improvecircuit integrationVSAvoidwithstand voltage detection
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent divides the circuit into separate functional areas: the snubber circuit is positioned on a first conductive pattern while the P and N electrodes are on a second conductive pattern. This spatial segmentation allows independent measurement of the snubber circuit's withstand voltage without interference from other high-voltage elements, resolving the contradiction between integration and measurement precision.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If the snubber circuit is provided on the same potential as P and N electrodes, then the manufacturing process is simplified, but the reliability of withstand voltage confirmation is reduced

Engineering Contradiction:
Improvecircuit fabricationVSAvoidwithstand voltage verification
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent introduces an insulating substrate as an intermediary between the snubber circuit and the P/N electrodes. This intermediate layer electrically isolates the snubber circuit from the high-voltage electrodes, enabling reliable withstand voltage measurement while maintaining a manufacturable structure through standard substrate fabrication processes.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If the snubber circuit uses a ceramic plate with resistance film, then the component integration is improved, but the measurement precision of withstand voltage remains insufficient

Engineering Contradiction:
Improvecomponent integrationVSAvoidwithstand voltage measurement
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent transitions from a two-dimensional integration approach to a three-dimensional layered structure. The ceramic plate with resistance film is positioned in a specific layer, separated from P and N electrodes by insulating substrates. This dimensional arrangement enables independent electrical measurement paths, achieving both component integration and precise withstand voltage measurement.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11610873B2Semiconductor device and method of manufacturing semiconductor device
Publication Date: 2023.03.21 MITSUBISHI ELECTRIC CORP
  • US11610873B2 patent drawing
  • US11610873B2 patent drawing
  • US11610873B2 patent drawing

AI summary

An object of the present disclosure is to provide a semiconductor device capable of confirming withstand voltage of a snubber circuit after providing the snubber circuit and a method of manufacturing the semiconductor device. A semiconductor device according to the present disclosure includes: an insulating substrate; a circuit patterns provided on the insulating substrate; a snubber circuit substrate provided on the insulating substrate separately from the circuit patterns; a resistance provided on one of the circuit patterns and the snubber circuit substrate; a capacitor provided on another one of the circuit patterns and the snubber circuit substrate; and at least one semiconductor element electrically connected to the resistance and the capacitor.