SOG Planarization via Two-Step Plasma Etch
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Solution Overview
Problem
Conventional etch-back methods for planarizing interlayer dielectric layers in semiconductor manufacturing result in non-uniformity due to varying etching rates across the wafer surface, particularly at the SOG/SiO2 interface, leading to reliability issues and residual metal fill problems.
Innovation Solution
A method involving a heat treatment followed by a two-step plasma etching process, where the first etch approaches the SOG/SiO2 interface and a second etch is performed at a controlled rate to achieve uniformity, using fluorocarbon-based or fluorine-based gases with oxygen to manage polymer effects and ensure equal etching rates across the interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional plasma etch-back method is used to remove SOG and planarize the ILD layer, then the etching process can be completed, but the etching rate varies between edge and center regions resulting in poor surface uniformity
Solution Approach 1:
The etching process is divided into multiple sequential steps with different gas chemistries: first using CF4-based plasma to etch through SOG, then switching to SF6-based plasma to etch through SiO2, and finally using a mixed gas plasma for precise interface planarization. This segmentation allows optimization of etching rates and selectivity for each material layer, resolving the uniformity issue while maintaining process manageability.
Solution Approach 2:
The patent changes multiple process parameters including gas composition (CF4, SF6, C4F8, O2 mixtures), pressure (1-100 mTorr range), power (50-500 W range), and temperature (room temperature to 400°C) to control polymer formation and etching rates. By dynamically adjusting these parameters between etching steps, the process achieves uniform etching across the wafer surface while managing the complexity through systematic parameter control.
2Productivity
If polymer is produced during SOG etch-back due to pressure difference in the etching chamber, then etching can proceed, but the amount of remaining polymer varies in different regions causing non-uniform etching rate
Solution Approach 1:
The patent controls pressure (1-100 mTorr) and introduces oxygen-containing gases (O2, CO, CO2, H2O) to manage polymer formation and removal. By adjusting these parameters, the process optimizes the balance between maintaining sufficient polymer for protection and removing excess polymer that causes non-uniform etching, thereby achieving both high productivity and uniformity.
Solution Approach 2:
Oxygen-containing gases (O2, CO, CO2, H2O) are introduced into the plasma process to oxidize and remove polymer residues from the etching chamber walls and wafer surface. This accelerated oxidation prevents polymer accumulation that would otherwise cause non-uniform etching rates, maintaining both productivity and precision.
3Manufacturing precision
If a two-step etching process is used to planarize the SOG/SiO2 interface, then better uniformity can be achieved, but the process time and complexity increase
Solution Approach 1:
The interface planarization is achieved through segmented etching steps: first CF4-based plasma etches SOG, then SF6-based plasma etches SiO2, and finally a mixed gas plasma performs precise interface planarization. This segmentation achieves superior uniformity by addressing each material's specific etching requirements, while the systematic approach keeps process time manageable through efficient step transitions.
Solution Approach 2:
The patent uses partial etching approaches where each step removes a portion of the required thickness, with the final interface planarization step providing the precise control needed. This partial action approach achieves excellent uniformity without requiring excessive process time, as each step is optimized to remove only the necessary amount of material.
4Productivity
If the etching rate at the edge is faster than in the center region, then the etching process completes quickly, but the non-uniformity is exacerbated and effective wafer area decreases
Solution Approach 1:
The patent uses pressure control (1-100 mTorr) and gas composition adjustment to manage the edge-enhanced etching effect. By optimizing these parameters, the process maintains high overall etching speed while reducing the excessive edge rate, achieving a balance between productivity and uniformity that maximizes effective wafer area.
Solution Approach 2:
Oxygen-containing gases are used to oxidize and remove polymer that accumulates preferentially at the wafer edge during etching. This prevents the edge from becoming overly protected and slowing down, while also preventing excessive edge etching by controlling polymer distribution, thereby maintaining both speed and uniformity across the wafer surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves surface uniformity, increasing the effective wafer area from 60% to at least 80% and reducing non-uniformity from 10% to 5%, resulting in a more reliable and planar semiconductor surface.
Implementation Method 1
a first etching is performed until approaching an interlayer interface of the stack structure; performing a second etching, until the top of the semiconductor structure is exposed
Implementation Method 2
using fluorocarbon-based or fluorine-based gases with oxygen to manage polymer effects
Implementation Method 3
performing a heat treatment on the stack structure to make it reflow
Data Source
AI summary
The invention discloses an etch-back method for planarization at the position-near-interface of an interlayer dielectric (ILD), comprising: depositing or growing a thick layer of SiO2 by the chemical vapor deposition or oxidation method on a surface of a wafer; spin-coating a layer of SOG and then performing a heat treatment to obtain a relatively uniform stack structure; perform an etch-back on the SOG using a plasma etching, and stopping when approaching the position-near-interface of SiO2; performing a plasma etch-back on the remaining SOG/SiO2 structure at the position-near-interface until achieving a desired thickness. Since a two-step etching at the position-near-interface is employed, an extremely good smooth surface of the ILD is obtained. That is, a planar and tidy surface of the ILD is obtained not only in the center region, but also even at the edge of the wafer.