SoC Address Translation Prefetch Mechanism
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Solution Overview
Problem
The existing system-on-chip (SoC) experiences significant performance degradation due to the long waiting time required to receive mapping information from a memory device for address translation, which affects the efficiency of memory management units (MMUs) in translating virtual addresses to physical addresses.
Innovation Solution
The implementation of a prefetch command mechanism that updates and stores mapping information in translation lookaside buffers (TLBs) ahead of time, reducing the waiting time for MMUs to load necessary data by proactively caching frequently accessed address blocks in both the first and second MMUs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If mapping information is loaded from memory device on demand, then memory bandwidth is conserved, but waiting time increases and system performance degrades
Solution Approach 1:
The system performs preliminary actions by detecting TLB update operations and proactively generating prefetch commands to load adjacent address block mapping information into the second TLB before it is actually needed. This advance preparation eliminates future waiting time when those address blocks are accessed, directly resolving the contradiction between reducing waiting time and maintaining system performance.
Solution Approach 2:
The address space is segmented into multiple address blocks, and the system selectively prefetches only adjacent blocks that are likely to be accessed next, rather than loading entire address spaces. This segmentation approach reduces the amount of data that needs to be prefetched, conserving memory bandwidth while still achieving the goal of reducing waiting time for specific address translations.
2Productivity
If mapping information is prefetched in advance, then waiting time is reduced, but memory bandwidth is consumed
Solution Approach 1:
The system performs preliminary actions by detecting TLB update operations and proactively generating prefetch commands to load adjacent address block mapping information into the second TLB before it is actually needed. This advance preparation eliminates future waiting time when those address blocks are accessed, directly resolving the contradiction between reducing waiting time and maintaining system performance.
Solution Approach 2:
The system applies partial action by prefetching only a limited scope of adjacent address blocks rather than entire address spaces. The prefetch command targets specific address blocks that are spatially adjacent to the currently accessed block, based on the understanding that adjacent addresses are more likely to be accessed next. This selective approach reduces memory bandwidth consumption compared to aggressive prefetching while still achieving significant waiting time reduction.
3Loss of time
If multiple MMUs access mapping information from memory device, then address translation is performed, but waiting time accumulates and performance degrades
Solution Approach 1:
The system merges the address translation operations of multiple MMUs by implementing a shared prefetching mechanism. When any MMU triggers a TLB update, the system generates prefetch commands that benefit all MMUs by pre-loading mapping information into the second TLB. This shared approach reduces the cumulative waiting time for multiple MMUs and improves overall system efficiency.
Solution Approach 2:
The system performs preliminary actions by detecting TLB update operations and proactively generating prefetch commands to load adjacent address block mapping information into the second TLB before it is actually needed. This advance preparation eliminates future waiting time when those address blocks are accessed, directly resolving the contradiction between reducing waiting time and maintaining system performance.
Data Source
AI summary
An operating method of a system-on-chip includes outputting a prefetch command in response to an update of mapping information on a first read target address, the update occurring in a first translation lookaside buffer storing first mapping information of a second address with respect to a first address, and storing, in response to the prefetch command, in a second translation lookaside buffer, second mapping information of a third address with respect to at least some second addresses of an address block including a second read target address.