SoC Address Translation for Power Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing System-on-a-Chip (SoC) technologies face challenges in efficiently supporting mobile applications while minimizing processor and memory usage within limited power consumption design specifications.
Innovation Solution
The proposed SoC includes a processor, a sub-processing circuit, and a memory system that utilizes a page table to map virtual addresses to either effective physical addresses or shadow physical addresses, allowing for direct or indirect access to memory, thereby optimizing resource usage and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor and memory usage are increased to support mobile applications, then the application performance is improved, but the power consumption increases
Solution Approach 1:
The patent segments the address space into virtual address space and physical address space, with further segmentation into effective physical address space and shadow physical address space. This segmentation allows the system to manage memory more efficiently by directing access patterns, thereby supporting mobile applications with improved performance while controlling power consumption through optimized memory access paths.
Solution Approach 2:
The patent introduces a page table as an intermediary mechanism between the virtual address space and physical address space. The page table enables indirect access to memory through shadow physical addresses, allowing the system to optimize memory bandwidth usage and reduce unnecessary memory transactions, thus improving application performance while minimizing power consumption.
2Adaptability or versatility
If the processor usage is increased to support mobile applications, then the application functionality is improved, but the device complexity increases
Solution Approach 1:
The patent implements a shadow physical address space that acts as a copy or mirror of the effective physical address space. This shadow copy allows the processor to access memory through an additional layer of abstraction without requiring increased processing power, as the shadow address translation can be managed through hardware-supported page table mechanisms rather than increasing overall processor complexity.
3Loss of energy
If the memory usage bandwidth is reduced to optimize power consumption, then the power efficiency is improved, but the data access speed may be affected
Solution Approach 1:
The patent implements a dynamic address translation mechanism where the system can switch between direct physical address access and shadow physical address access based on the access pattern. This dynamic approach allows the system to optimize for power efficiency by using shadow addresses for certain access patterns while maintaining fast data access speeds by using direct addresses for other patterns, thus balancing power efficiency and access speed.
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
An application processor, a System-on-a-Chip (SoC) (100), and a method of operating the same are provided. The SoC includes a first processor (110) outputting a first access address, a system bus (160) configured to transmit an access address to a memory (130) if the access address, which is received from the first processor (110) corresponds to a physical address area of the memory (130), and to transmit the access address to other processing circuits other than the memory (130) if the access address corresponds to a shadow physical address area other than the physical address area of the memory (130), and a sub-processing circuit (120) receiving the first access address from the first processor (110) via the system bus (160), converting the first access address into a second access address corresponding to the physical address area, and transmitting the second access address to the system bus (160) to access the memory (130).