SoC Address Translation for Storage DMA Efficiency
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Solution Overview
Problem
The existing data transmission methods in converged infrastructure scenarios face inefficiencies and delays due to the need for two DMA migrations between the SoC and storage medium, consuming CPU and memory resources and resulting in low data transmission efficiency.
Innovation Solution
A data transmission method utilizing an extended PCIe bus for communication between the processor, SoC, and storage medium, where the SoC translates addresses and forwards data using the storage medium's DMA controller, eliminating the need for SoC involvement in DMA migrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two DMA migrations are performed through SoC for data transmission between processor and storage medium, then data can be transmitted between different memory address spaces, but transmission delay increases and transmission efficiency decreases
Solution Approach 1:
The patent extracts the SoC from the DMA migration path by enabling the storage medium's DMA controller to perform direct address translation and data migration using the extended PCIe bus. This removes the SoC as an intermediate环节, eliminating the need for two-segment DMA migrations and reducing transmission delay while maintaining address space compatibility.
Solution Approach 2:
The extended PCIe bus serves as a new intermediary that enables direct communication between the processor and storage medium, bypassing the SoC. This mediator provides both address translation capabilities and DMA control functions, allowing direct data migration without requiring SoC involvement and thus reducing transmission time.
2Adaptability or versatility
If SoC participates in DMA migration for multiple storage media, then data transmission between processor and multiple storage devices is enabled, but CPU and memory resources are consumed
Solution Approach 1:
The storage medium's DMA controller is empowered to perform address translation and data migration autonomously without requiring SoC intervention. Each storage medium can independently manage its own DMA operations, eliminating the need for SoC to coordinate multiple storage devices and thereby reducing CPU and memory resource consumption while maintaining multi-device support.
Solution Approach 2:
The patent segments the DMA control functionality from the SoC and assigns it to individual storage media's DMA controllers. This segmentation allows each storage medium to independently handle its own data transmission, eliminating the resource bottleneck at the SoC level and reducing overall system resource consumption while supporting multiple storage devices.
3Adaptability or versatility
If two DMA migrations are performed through SoC, then data can be transferred between processor memory and storage medium, but device complexity increases
Solution Approach 1:
The patent merges the address translation function and DMA control function into the storage medium's DMA controller. By combining these functions that were previously distributed across the processor and SoC into a single integrated controller at the storage medium, the system simplifies the data transmission path from processor to storage medium while maintaining full data transmission capability.
Data Source
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AI summary
A data transmission method, an apparatus, a device, and a system are provided. The method includes: obtaining, by an SoC (202), a first request message, where the first request message includes a first address of a storage medium (203) and an operation type, and the first address is an address assigned by a processor (201) to the storage medium (203) in a memory address managed by the processor; determining a second address based on the first address and generating a second request message, where the second address is an address assigned by the SoC (202) to the storage medium (203) in a memory address managed by the SoC; sending a first control instruction to a DMA controller of the storage medium (203) according to the second address, where the first control instruction is used to instruct the DMA controller to obtain the second request message; and in a case of a read operation, receiving first data sent by the DAM controller, and sending the first data to the processor (201); or in a case of a write operation, receiving second data sent by the processor (201), and sending the second data to the DMA controller.