Worst-Case Timing Analysis for SoC Aging Effects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
System-on-chip (SoC) chip reliability is compromised by aging-induced defects such as Hot Carrier Injection, Electron-Migration, Negative Bias Temperature Instability, and Time Dependent Dielectric Breakdown, which are currently addressed through worst-case design assumptions and resource-intensive simulation tools like HSPICE.
Innovation Solution
A method to analyze and identify worst and best-case scenarios of DC vector forms in logic circuits without performing circuit simulations, using timing paths and Boolean expressions to determine stressed transistors and calculate aging costs efficiently, thereby optimizing design margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If worst-case design assumptions are used to address aging-induced defects, then reliability is improved, but device complexity and design margins are worsened due to over-design
Solution Approach 1:
The patent changes the parameter of aging cost calculation from worst-case assumptions to actual usage-based DC vector analysis. By evaluating aging costs based on real operating conditions (different DC vectors representing different usage scenarios) rather than worst-case assumptions, the method achieves reliable aging prediction without requiring excessive design margins or complex over-design.
2Measurement precision
If full circuit simulations are performed to analyze aging effects, then measurement precision is improved, but productivity and computational efficiency are worsened
Solution Approach 1:
The patent extracts the essential aging analysis from full circuit simulations by focusing only on DC vector forms and their impact on aging costs. Instead of performing complete circuit simulations, the method extracts and evaluates only the relevant DC vector characteristics, achieving accurate aging effect analysis with significantly reduced computational resources.
Solution Approach 2:
The patent creates a simplified model that copies only the essential aging-related characteristics from the full circuit. By representing aging effects through DC vector forms and their associated costs rather than complete circuit behavior, the method achieves precise aging analysis without the computational burden of full simulations.
3Reliability
If resource-intensive simulation tools are used to analyze aging-induced defects, then reliability analysis accuracy is improved, but loss of time and computational resources are worsened
Solution Approach 1:
The patent applies partial action by performing only the necessary DC vector analysis required for aging cost evaluation, rather than executing complete circuit simulations. This partial analysis approach focuses computational effort only on the aspects directly relevant to aging effects, achieving accurate reliability analysis with significantly reduced time and resource consumption.
Data Source
AI summary
A method includes: identifying a timing path of a logic circuit; determining a Boolean expression at an internal node in the timing path; providing a DC vector having a plurality of forms; determining a Boolean value at the internal node for each of the forms based on the Boolean expression; determining a quantity of stressed transistors in the timing path for each of the forms separately based on the respective Boolean value; and determining a best-case form, associated with an aging effect of the logic circuit, and a worst-case form, associated with the aging effect, out of the forms based on the quantities of stressed transistors.