SoC Algorithm Validation via Design of Experiments

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Solution Overview

Problem

Existing System on Chip (SoC) technologies lack an efficient method for validating new algorithm or system versions, which can lead to adverse operational effects if not properly tested for functional equivalence and performance compared to existing versions.

Innovation Solution

The implementation of a Design of Experiments (DoE) processing technique to compare outputs from both the new and existing algorithms or systems by modifying predetermined inputs, allowing for the determination of significant functional differences and characterization of performance, using a validation engine that executes and compares the algorithms or systems within the SoC.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a new version of an algorithm is deployed to replace an existing version in an SoC, then new functionality or bug fixes are introduced, but operational stability and functional equivalence cannot be guaranteed without proper validation

Engineering Contradiction:
Improvealgorithm functionalityVSAvoidoperational stability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies preliminary action by performing validation testing of the new algorithm version before it is deployed to replace the existing version. The validation engine executes the new algorithm with predetermined test inputs and compares outputs against the existing algorithm's behavior, ensuring functional equivalence is confirmed in advance, thereby preventing operational instability after deployment

Inventive Principle:
Principle #10Preliminary action

2Reliability

If comprehensive validation testing is performed to ensure functional equivalence between algorithm versions, then operational reliability is maintained, but validation time and processing resources are consumed

Engineering Contradiction:
Improvefunctional equivalenceVSAvoidvalidation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial action by using a predetermined set of test inputs that are carefully selected to be representative of actual operating conditions. Rather than testing all possible inputs, the validation engine uses this optimized subset to efficiently determine functional equivalence, reducing validation time while maintaining reliability

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent applies parameter changes by modifying predetermined inputs to the algorithm and observing output variations. The validation engine systematically varies input parameters and compares how both the existing and new algorithms respond, enabling efficient detection of functional differences through controlled parameter experimentation

Inventive Principle:
Principle #35Parameter changes

3Productivity

If the existing algorithm version is replaced with a new version without validation, then deployment speed is increased, but adverse operational effects may occur

Engineering Contradiction:
Improvedeployment speedVSAvoidadverse operational effects
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary anti-action by implementing a validation mechanism that proactively identifies and prevents adverse operational effects before they can occur in production. The validation engine detects functional differences between algorithm versions and blocks deployment if equivalence cannot be confirmed, thereby preventing harmful effects while maintaining relatively fast deployment through automated testing

Inventive Principle:
Principle #9Preliminary anti-action

Data Source

PatentUS8856597B2Validation of a system using a design of experiments processing technique
Publication Date: 2014.10.07 STMICROELECTRONICS INT NV
  • US8856597B2 patent drawing
  • US8856597B2 patent drawing
  • US8856597B2 patent drawing

AI summary

A validation system includes a test block that operates to apply a set of inputs to a system under test, such as a test system or an executable test algorithm, and receive from said system under test a first set of outputs produced by operation of the system under test in response to application of the set of inputs. The first set of outputs, as well as a second set of outputs reflecting output produced by operation of a reference system or executable reference algorithm in response to application of the same set of inputs, is processed to make a validation determination. A validation processing block compares the first and second sets of outputs to validate the system under test as an equivalent to the reference system.