SOC Always-On Domain Wake-Up Detection
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Solution Overview
Problem
Current low power mode (LPM) designs for electronic devices, such as data storage devices, face challenges in reducing power consumption while maintaining the ability to detect wake-up commands and resume normal operation, often requiring additional hardware and complex power management interfaces, which increase cost and power consumption.
Innovation Solution
A system-on-chip (SOC) with an always-on domain (AOD) power island and a power control block that monitors for wake-up signals using an energy detector and qualification logic, allowing the device to power down and resume operation efficiently without external control circuitry, utilizing a main power switch to manage power supply to different regions of the SOC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional hardware and complex power management interfaces are used to detect wake-up commands in low power mode, then the device can maintain wake-up detection capability, but hardware complexity and cost increase
Solution Approach 1:
The SOC uses its own existing PHY interface circuitry to detect wake-up commands during low power mode, eliminating the need for separate detection hardware. The PHY interface, which normally handles data communication, is repurposed to monitor for wake-up signals, allowing the device to self-manage wake-up detection without additional external control circuitry.
Solution Approach 2:
The PHY interface is designed to serve multiple functions: normal data communication during active mode and wake-up command detection during low power mode. This multi-functionality allows a single hardware component to handle both operational requirements, reducing overall hardware complexity while maintaining both communication and wake-up detection capabilities.
2Reliability
If additional hardware and complex power management interfaces are used to detect wake-up commands, then wake-up detection can be maintained, but power consumption increases
Solution Approach 1:
The SOC leverages its existing PHY interface to perform wake-up detection, avoiding the power overhead of dedicated detection circuitry. By using the same interface that would be used for normal communication, the device incurs minimal additional power consumption to maintain wake-up detection capability during low power mode.
Solution Approach 2:
The PHY interface handles both data communication and wake-up detection functions, consolidating power consumption into a single existing circuit rather than adding separate powered detection hardware. This approach ensures that wake-up detection capability is maintained with minimal incremental power overhead.
3Use of energy by moving object
If power is completely cut off to reduce power consumption, then power savings are maximized, but the device cannot detect wake-up commands or resume operation
Solution Approach 1:
The SOC is divided into at least two power domains: a low power mode domain where most functionality is powered down, and an always-on domain that maintains the PHY interface and wake-up detection capability. This segmentation allows selective power management where critical wake-up detection functions remain powered while non-essential functions are powered down, achieving both low power consumption and maintained wake-up capability.
4Ease of operation
If external control circuitry is used to manage power and detect wake-up signals, then power management capability is maintained, but hardware complexity and cost increase
Solution Approach 1:
The SOC performs its own power management and wake-up detection internally using integrated PHY interface circuitry, eliminating the need for external control circuitry. The device autonomously monitors for wake-up commands and manages power state transitions without requiring external intervention, reducing overall system hardware complexity while maintaining full power management capability.
Data Source
AI summary
Apparatus and method for supplying electrical power to a device. A system on chip (SOC) integrated circuit includes a first region having a processing core and a second region characterized as an always on domain (AOD) power island having a power control block with an energy detector coupled to a host input line. First and second power supply modules respectively supply power to the first and second regions. The second power supply module includes a main switch between the first power supply module and a host input voltage terminal. The power control block opens the main switch to enter a low power mode during which no power is supplied to the first region, and the power control block closes the main switch to resume application of power to the first region responsive to the energy detector detecting electrical energy on the host input line.