Multi-Master SoC Arbitration Using Segmented Priority Encoders
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Solution Overview
Problem
In multi-core systems, shared resources like SRAM introduce latency and limit maximum clock speed due to long timing paths created when multiple masters access the same resource, making it challenging to achieve higher clock speeds with simple arbitration schemes.
Innovation Solution
A multi-master system on chip (SoC) that incorporates a next state generator and round robin pointer to manage priority encoding and grant signals, ensuring that priority is maintained for one master until a request is made by another, combining fixed priority and round robin arbitration to minimize combinational paths and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If simple fixed priority or round robin arbitration scheme is used, then the system is easy to implement, but long timing paths are created that limit maximum clock speed
Solution Approach 1:
The arbitration logic is segmented into separate priority encoders for different masters, with each encoder handling only its own master's requests. This segmentation breaks the long timing paths that would otherwise exist from one master to another through a single centralized arbitration unit, thereby enabling higher clock speeds while maintaining implementation simplicity.
2Adaptability or versatility
If multiple masters access the same shared resource, then resource sharing is achieved, but long timing paths are created from one master to another that limit maximum clock speed
Solution Approach 1:
The arbitration logic is segmented into separate priority encoders for different masters, with each encoder handling only its own master's requests. This segmentation breaks the long timing paths that would otherwise exist from one master to another through a single centralized arbitration unit, thereby enabling higher clock speeds while maintaining implementation simplicity.
Solution Approach 2:
A next state generator acts as an intermediary between the priority encoders and the round robin pointer. It receives grant signals from priority encoders and generates the next state of the round robin pointer without creating long timing paths between masters, thus mediating the interaction while preserving high clock speed operation.
3Reliability
If priority is maintained for one master until another requests access, then fair arbitration is achieved, but the arbitration logic becomes more complex
Solution Approach 1:
The patent merges fixed priority arbitration and round robin arbitration into a unified system. Priority encoders provide fixed priority within each master, while the round robin pointer ensures fair access across different masters by cycling through them. This combination achieves fair arbitration without requiring complex state machines or additional control logic.
Solution Approach 2:
The round robin pointer serves multiple functions: it enables priority encoders in a cyclic manner, tracks which masters have been served, and determines the next master to be granted access. This multi-functionality reduces the need for separate control mechanisms, thereby limiting the increase in complexity while maintaining arbitration fairness.
Data Source
AI summary
A multi master system on chip (SoC) includes a plurality of masters comprising a first master and a second master, each configured to generate a request. A next state generator in the multi master SoC is configured to generate a next state of a round robin pointer in response to the request and a current state of the round robin pointer. The round robin pointer is configured to generate an enable signal to enable a priority encoder for the first master in response to the current state of the round robin pointer. Further, the next state of the round robin pointer is generated such that a priority is maintained for the first master until there is a request from the second master.