Back Power Protection Logic for SOC Baseband Reliability
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Solution Overview
Problem
In complex electronics systems like smartphones and laptops, the inter-process communication and control signaling among various chips on a System on a Chip (SOC) can be disrupted during transient events, leading to signal corruption and hardware faults like CMOS latchup, especially when devices transition to a power-collapsed state, requiring additional hardware and software complexity to prevent back power feed and ensure proper system operation.
Innovation Solution
Implementing back power protection (BPP) by transmitting supply outputs from two power management integrated circuits (PMICs) to a logical OR function, generating a composite power signal, and using it to manage input/output logic levels, along with an automatic power back-feed prevention circuit and a time-critical alert signal to prevent CMOS latchup and data corruption, independent of data bus communication protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional hardware components are added to prevent back power feed and ensure proper system operation during transient events, then system reliability improves, but device complexity increases
Solution Approach 1:
The patent introduces a logical OR function as an intermediary component that combines BPP signals from multiple PMICs. This mediator processes the power status information and generates a composite BPP signal that protects the baseband processor without requiring complex control logic in each individual PMIC, thus improving reliability while managing device complexity.
Solution Approach 2:
The BPP rail serves multiple functions: it carries power supply information from PMICs to the logical OR function, transmits the composite BPP signal to the baseband processor, and provides a pathway for time-critical alert signals. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby improving reliability without proportionally increasing device complexity.
2Reliability
If complex control signaling and additional hardware are implemented to prevent CMOS latchup and data corruption during power transitions, then system reliability improves, but hardware complexity increases
Solution Approach 1:
The logical OR function acts as a simplified intermediary that automatically generates the composite BPP signal based on the power status of multiple PMICs. This eliminates the need for complex control signaling between PMICs and the baseband processor, preventing CMOS latchup and data corruption through a simple, reliable hardware logic function rather than complex control sequences.
Solution Approach 2:
The BPP system is designed to be self-regulating through the logical OR function that automatically responds to power status changes from any PMIC. The system self-adjusts the composite BPP signal based on the power states of connected processors, providing automatic protection against transient events without requiring external intervention or complex control logic.
3Reliability
If separate BPP rails with automatic power back-feed prevention circuits are used for each PMIC, then protection against power back-feed improves, but device complexity increases
Solution Approach 1:
The patent divides the BPP protection function into separate segments: each PMIC has its own dedicated BPP rail with automatic power back-feed prevention, and a logical OR function that combines these segmented signals. This segmentation allows each PMIC to be independently protected while maintaining overall system simplicity through the unified logical OR combination, improving protection effectiveness without excessive complexity.
Solution Approach 2:
The patent merges multiple separate BPP signals from different PMICs into a single composite BPP signal through the logical OR function. This combining approach consolidates the protection functionality, allowing the baseband processor to receive a unified protection signal that reflects the power status of all connected PMICs, thereby improving protection while reducing the complexity of managing multiple independent control circuits.
Data Source
AI summary
Aspects of the disclosure are directed to a System on a Chip (SOC). In accordance with one aspect, a method for implementing back power protection (BPP) in a SOC includes transmitting a first back power protection (BPP) supply output from a first power management integrated circuit (PMIC) to a logical OR function; transmitting a second back power protection (BPP) supply output from a second power management integrated circuit (PMIC) to the logical OR function; using the logical OR function to generate a composite BPP power based on the first BPP supply output and the second BPP supply output; and inputting the composite BPP power to a baseband processor (BP), wherein the baseband processor (BP) is coupled to the second PMIC.