Master-Slave SoC Boot Code Encryption and Distribution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The complexity and size of systems with multiple System-on-Chips (SoCs) increase costs due to the need for multiple chips for non-volatile memory devices and controllers for storing and decrypting boot code, compromising system reliability.
Innovation Solution
A processor configuration with semiconductor integrated circuits where one chip serves as a master and others as slaves, with encrypted boot code and route information being transmitted and decrypted within the slave chips, eliminating the need for separate memory units and controllers for each slave chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each SoC is provided with a non-volatile memory device and controller for storing and decrypting boot code, then system reliability is improved, but the number of elements increases leading to increased costs
Solution Approach 1:
The patent combines the non-volatile memory device and controller into a single integrated chip. The memory device stores encrypted boot code, and the controller on the same chip decrypts and executes it, eliminating the need for separate memory units and controllers for each slave chip while maintaining security and reliability
Solution Approach 2:
The master chip serves multiple functions: it stores encrypted boot code for all slave chips, decrypts the boot code, and distributes it to slave chips. This multi-functional approach eliminates the need for each slave chip to have its own dedicated memory and controller, reducing overall system complexity
2Reliability
If separate memory units and controllers are provided for each slave chip, then boot code security is improved, but manufacturing costs increase
Solution Approach 1:
The memory device and controller are merged into a single integrated chip, reducing the total number of components that need to be manufactured and assembled. This integration maintains security through encrypted boot code storage and decryption while lowering manufacturing costs by reducing component count
3Reliability
If multiple chips are used for memory and controllers, then system security is improved, but the system size and complexity increase
Solution Approach 1:
By integrating the memory device and controller into a single chip, the physical footprint is reduced compared to using separate chips for each component. The master chip stores encrypted boot code and performs decryption, eliminating the need for additional memory chips and controller chips that would increase system size
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A first semiconductor integrated circuit of a processing apparatus, the first semiconductor integrated circuit comprising: a communication circuit configured to: generate a second boot code by encrypting a first boot code, wherein the first boot code comprises: a third boot code to be used by a second semiconductor integrated circuit of the processing apparatus to perform a boot process, and a fourth boot code to be used by a third semiconductor integrated circuit of the processing apparatus to perform a boot process, transmit, based on first route information indicating a delivery route of the second boot code, first data including the second boot code and the first route information to the second semiconductor integrated circuit via a first network, wherein the second semiconductor integrated circuit is configured to serve as a first destination, and receive, from the first destination, an acknowledgement signal indicating that receipt of the first data is completed; and a control circuit configured to be connected to the communication circuit via a system bus, and cause, when the communication circuit receives the acknowledgement signal, the communication circuit to transmit, to the first destination via the first network, a boot instruction signal instructing the first destination to perform a boot process based on the first boot code.