SoC Boot Device DMA Interface Parameter Configuration
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Solution Overview
Problem
Existing boot devices for SoC chips lack flexibility in processor environments due to fixed bus interface parameters and the absence of a Direct Memory Access (DMA) interface, resulting in low transmission efficiency and inadequate booting speed, which affects both chip-level and system-level performance.
Innovation Solution
A boot device for SoC chips incorporating a memory interface module, a DMA bus interface module, a boot processing module, and a parameter configuration module, which includes a bus interface configuration module, a DMA configuration module, and an operation command configuration module to configure parameters for efficient data transfer and improve booting efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed bus interface parameters are used in boot devices, then device simplicity is maintained, but adaptability to different processor environments deteriorates
Solution Approach 1:
The patent applies the Dynamics principle by making the bus interface parameters dynamic and configurable rather than fixed. The boot device includes a parameter configuration module that can set data bus bit width, address bus bit width, burst transmission type, and burst transmission length according to different processor environments. This allows the device to adapt its interface parameters dynamically to match various processor requirements while maintaining a relatively simple base structure.
2Productivity
If DMA interface is not included in boot devices, then device complexity is reduced, but transmission efficiency deteriorates
Solution Approach 1:
The patent applies the Universality principle by integrating multiple functions into the boot device, including the DMA (Direct Memory Access) interface. The DMA interface enables high-speed data transfer between external memory and the processor without occupying processor time, while the device also performs boot processing and parameter configuration functions. This multi-functional design achieves high transmission efficiency while keeping the overall device structure integrated and manageable.
3Adaptability or versatility
If transmission addresses cannot be configured, then device simplicity is maintained, but adaptability to different memory configurations deteriorates
Solution Approach 1:
The patent applies the Parameter changes principle by making transmission addresses configurable parameters. The parameter configuration module can set the transmission destination address and data transmission length according to different memory configurations and processor requirements. This allows the boot device to adapt to various memory arrangements and sizes while maintaining a unified device structure that can be configured for different applications.
Data Source
Figure 1~2
AI summary
A boot device for a System on Chip (SoC) chip is disclosed. The device includes a memory interface module (10) which is provided with a memory bus interface and configured to connect with an external memory (50); a Direct Memory Access (DMA) bus interface module (20) which is provided with a DMA bus interface (60) configured to transfer the data in the external memory (50) to the storing space which the destination address is corresponding to; a boot processing module (30) is connected with the memory interface module (10) and the DMA bus interface module (20) respectively, which is configured to send the data reading and writing commands to the external memory (50) through the memory interface module (10) and transform the data transferred by the external memory (50) to the data matched with the DMA bus interface module (20); a parameter configuration module (40) is configured to configure the parameters for the DMA bus interface module (20), the memory interface module (10) and the boot processing module (30). A SoC chip is disclosed. The boot device or the SoC chip can improve the booting efficiency and improve the system performance of the SoC chip.