SoC Boot Sequencing for Priority Peripheral Activation

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Solution Overview

Problem

Existing integrated circuits (ICs) face challenges in rapidly enabling high-priority functionality due to varying configuration times of different circuits during the boot process, especially in systems requiring secure software execution or data handling.

Innovation Solution

The IC boot process is optimized by configuring phase locked loops (PLLs) out of bypass mode early, using secondary and tertiary boot loaders to streamline activation of necessary peripherals, and grouping peripherals into devgroups for parallel execution, enabling secure and public memory initialization, and managing clock and power structures to accelerate time-critical functions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all circuit elements are initialized during boot, then complete system functionality is achieved, but boot time increases

Engineering Contradiction:
Improvesystem functionalityVSAvoidboot time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The boot process is segmented into multiple stages with different initialization priorities. Critical circuit elements required for high-priority functionalities are initialized first, while non-critical elements are initialized later or skipped entirely during boot. This segmentation allows the system to achieve functional adequacy without completing full initialization, thereby reducing boot time while maintaining essential system reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies partial action by initializing only the subset of circuit elements necessary to achieve the desired high-priority functionality, rather than initializing all circuit elements. The operational data explicitly specifies which circuit elements to initialize, enabling the system to perform sufficient initialization without the overhead of complete initialization, thus reducing boot time while maintaining adequate system functionality.

Inventive Principle:
Principle #16Partial or excessive action

2Reliability

If circuit elements are initialized in default order, then initialization completeness is ensured, but time-critical functions are delayed

Engineering Contradiction:
Improveinitialization completenessVSAvoidactivation speed of time-critical functions
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent implements preliminary action by pre-determining the initialization sequence based on functional priority before the boot process begins. The operational data, generated during design or configuration, specifies which circuit elements should be initialized first based on their importance to high-priority functionalities. This preliminary planning ensures that time-critical functions receive priority initialization, accelerating their activation speed while maintaining initialization completeness for essential elements.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Different initialization strategies are applied to different circuit elements based on their local quality or importance. Critical circuit elements associated with high-priority functionalities receive immediate initialization with full resources, while non-critical elements are initialized later or with reduced resources. This differentiated approach ensures that time-critical functions are activated rapidly without compromising the eventual completeness of initialization for all elements.

Inventive Principle:
Principle #3Local quality

3Device complexity

If peripheral activation is performed sequentially, then resource management is simplified, but boot process duration increases

Engineering Contradiction:
Improveresource management complexityVSAvoidboot process duration
Core Design Contradiction:
Device complexityVSDuration of action of moving object

Solution Approach 1:

The peripheral activation process is segmented into parallel initialization tasks based on resource dependencies. The operational data identifies groups of peripherals that can be initialized simultaneously without conflicting for shared resources. By dividing the activation process into independent parallel segments, the system achieves faster overall boot duration while maintaining manageable resource control through the predefined segmentation strategy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent merges multiple peripheral initialization operations into parallel execution streams where possible. Peripherals with independent resource requirements are combined into simultaneous initialization sequences, executing multiple activation tasks at the same time rather than sequentially. This merging of operations significantly reduces the total boot process duration while the operational data ensures proper resource allocation and coordination across the parallel streams.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12493700B2Integrated circuit with accelerated boot to priority function
Publication Date: 2025.12.09 TEXAS INSTRUMENTS INC
  • US12493700B2 patent drawing
  • US12493700B2 patent drawing
  • US12493700B2 patent drawing

AI summary

In described examples, a method of operating a system on chip (SoC) includes the following steps. Receive a component description that describes connections among circuit elements of the SoC. Receive a list of specified peripherals to activate while the SoC boots. Receive a hint data that describes a bypass mode clock frequency of a phase locked loop (PLL) of the SoC. Determine an operational data in response to the component description, the hint data, and the specified peripherals. The operational data specifies a subset of the circuit elements required to make the specified peripherals operational. Initialize, and limit the initializing, to the subset of the circuit elements.