SoC Boot Code Translation Unit for Off-Chip Flash Memory
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Solution Overview
Problem
The existing systems for System on a Chip (SoC) require time-consuming and costly tape-outs for boot code changes due to the need for complex chip packaging and high pin-count interfaces for off-chip flash memory, which complicates post-tape out modifications and increases manufacturing costs.
Innovation Solution
Implementing an on-board translation unit that translates bus protocol commands into a sequence usable by a low pin-count serial interface to read boot code from an off-chip non-volatile memory device, allowing for post-tape out changes without subsequent tape-outs and reducing signal pin counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If boot code is stored in on-chip ROM, then the SoC has simple packaging and low manufacturing cost, but any changes to boot code require time-consuming subsequent tape-outs
Solution Approach 1:
The patent divides the boot code storage into two parts: a fixed on-chip ROM containing the base boot code, and a separate off-chip flash memory device containing updatable boot code sections. This segmentation allows the boot code to be flexible and updatable without requiring changes to the main SoC chip structure, resolving the contradiction between manufacturing simplicity and code adaptability.
Solution Approach 2:
The patent introduces an intermediary translation unit that translates bus protocol commands into commands suitable for the serial interface to read boot code from off-chip flash memory. This intermediary mechanism enables boot code updates from external memory without requiring complex packaging or high pin-count interfaces, maintaining manufacturing simplicity while providing code flexibility.
2Adaptability or versatility
If boot code is stored in off-chip flash memory device, then boot code can be changed post-tape out, but chip packaging becomes more complex and manufacturing costs increase
Solution Approach 1:
The patent makes the serial interface serve multiple functions: it not only communicates with peripheral devices but also enables reading boot code from off-chip flash memory. By making the serial interface multi-functional, the patent avoids adding dedicated complex interfaces for boot code updates, thereby reducing packaging complexity while maintaining boot code flexibility.
Solution Approach 2:
The translation unit acts as an intermediary that bridges the bus protocol and the serial interface protocol, enabling the system to read boot code from off-chip flash memory through the existing serial interface. This intermediary mechanism simplifies packaging by eliminating the need for dedicated high pin-count flash interfaces while still providing post-tape out boot code change capability.
3Adaptability or versatility
If off-chip flash memory is connected via high pin-count interface, then boot code can be read from off-chip device, but board costs and manufacturing costs increase
Solution Approach 1:
The patent changes the interface parameter from high pin-count parallel interface to low pin-count serial interface. By changing the communication parameter to serial transmission, the patent significantly reduces the number of pins required while still enabling boot code reading from off-chip flash memory, thereby reducing manufacturing costs while maintaining boot code accessibility.
Solution Approach 2:
The translation unit serves as an intermediary that enables the low pin-count serial interface to perform the function of reading boot code from off-chip flash memory. This intermediary mechanism allows the system to use the simpler, lower-cost serial interface instead of requiring complex high pin-count interfaces, thus reducing manufacturing costs while maintaining boot code accessibility.
Data Source
AI summary
Translation of boot code read request commands from an on-board processor of a system on a chip (SoC) from a bus protocol (e.g., advanced high-performance bus (AHB) protocol) into a sequence of commands understandable by a serial interface of the SoC to read boot code from an off-board (e.g., flash or other non-volatile) memory device. The serial interface of the memory device may include a relatively low pin count (e.g., 5 pins) and boot code of the memory device may be modified after tape-out of the SoC free of necessitating a subsequent tape-out of the SoC.