SOC Boundary Model Extraction for ATPG Runtime Reduction
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Solution Overview
Problem
Current methods for testing system on a chip (SOC) designs, which include multiple intellectual property (IP) cores, face challenges such as increased model size and runtime, reduced accuracy in interconnect fault coverage, and limitations in simulating test patterns due to the inclusion of full IP core internal logic, leading to inefficiencies and infeasibility in three-dimensional designs.
Innovation Solution
A method for generating a reduced gate-level boundary model by using wrapper cells and controller logic to extract boundary and controller logic, allowing for the creation of a more accurate and efficient model that separates interconnect logic from IP core internal logic, enabling automated test pattern generation and simulation without requiring a complete SOC model.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the full IP core model is included in the ATPG model along with interconnect logic, then the completeness of the test model is improved, but the model size and runtime for ATPG increase significantly
Solution Approach 1:
The patent segments the test model into two distinct parts: (1) the full IP core models with their internal logic, and (2) the interconnect and glue logic. The IP core test patterns are generated separately using the full IP core models, while the interconnect test uses a simplified model that excludes IP core internal logic. This segmentation allows comprehensive testing without the computational burden of including all IP core logic in the interconnect ATPG model.
Solution Approach 2:
The patent extracts and removes the IP core internal logic from the interconnect ATPG model. By taking out the unnecessary IP core internal logic gates while retaining the interconnect and glue logic, the model size is dramatically reduced. The extracted IP core test patterns are then applied separately to the full IP core models, achieving complete test coverage without the runtime penalty of a monolithic model.
2Reliability
If the full IP core model is included in the ATPG model, then the completeness of the test model is improved, but the accuracy of interconnect fault coverage is reduced due to bookkeeping complexity
Solution Approach 1:
The patent segments the fault analysis into two separate domains: IP core internal faults and interconnect faults. By separating these domains, the patent eliminates the bookkeeping complexity that arises from trying to track which faults belong to which IP core versus the interconnect. Each domain is analyzed independently with appropriate test patterns, improving the accuracy of interconnect fault coverage measurements.
Solution Approach 2:
The patent extracts the IP core internal logic from the interconnect ATPG model, removing the source of bookkeeping complexity. This extraction allows for clean separation of fault domains, where interconnect faults are analyzed in isolation without the confusion of IP core internal logic. The accuracy of interconnect fault coverage is thereby improved by eliminating the mixing of fault types in a single monolithic model.
3Measurement precision
If the full SOC model is built for simulation of test patterns, then the accuracy of simulation is improved, but the database size and runtime required for simulation increase hugely
Solution Approach 1:
The patent segments the simulation process into two independent simulation phases: (1) IP core simulation using full IP core models with their internal logic, and (2) interconnect simulation using a simplified model without IP core internal logic. This segmentation dramatically reduces the database size required for interconnect simulation while maintaining accuracy for interconnect fault detection. The full IP core models are only simulated when necessary for IP core-specific test validation.
Solution Approach 2:
The patent extracts the IP core internal logic from the interconnect simulation model, removing the excessive database requirements for full SOC simulation. By taking out the redundant IP core internal logic from the interconnect simulation, the database size is reduced while the simulation accuracy for interconnect faults is preserved. The extracted IP core models are simulated separately only when needed.
4Reliability
If complete ATPG models are created for all embedded dies in three-dimensional designs, then the test coverage is improved, but the model size becomes infeasibly large
Solution Approach 1:
The patent segments the three-dimensional design model into individual die-level components, where each die is represented by its interconnect and glue logic without the internal logic of embedded IP cores. This segmentation allows for comprehensive interconnect testing across multiple dies while keeping each die's model size manageable. The full IP core models are retained separately for IP core-specific testing, achieving complete test coverage without infeasible model sizes.
Solution Approach 2:
The patent extracts the internal logic of embedded IP cores from the die-level models in three-dimensional designs. By removing the IP core internal logic from the interconnect ATPG models, the model size becomes feasible for three-dimensional designs with multiple stacked dies. The extracted IP core models are tested separately, ensuring complete test coverage while maintaining manageable model sizes for interconnect analysis.
Data Source
AI summary
SOC designs increasingly feature IP cores with standardized wrapper cells having vendor-provided test patterns for the internal logic. To test wrapper, interconnect, and other boundary logic, a boundary model is extracted from the design in a synthesis or ATPG environment. Wrapper cells are identified and boundary logic extracted by structural tracing of wrapper chains and tracing from core inputs/outputs to the wrapper cells. A created boundary model excludes core internal logic tested by vendor-provided test patterns to be migrated to the containing chip interface. An SOC ATPG model is built including boundary models for all embedded cores, interconnects, and any other logic residing at the SOC top hierarchical level. This model is very compact yet accurate for testing logic external to all embedded cores. Test time is reduced and test pattern generation greatly simplified, while featuring good test coverage. The same approach is used for 3D packages having multiple dies.