Adaptive SOC Bridge Latency for Data Integrity
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Solution Overview
Problem
System-on-a-chip (SOC) bridge delays can lead to data corruption due to premature assumption of data transfer completion, and existing solutions either result in corrupted data or significant performance reduction by introducing unnecessary latency.
Innovation Solution
An SOC bridge module that applies an adaptive delay to data transfers, monitored by inbound and outbound transfer monitors, ensuring data integrity by inserting wait states only until the data is confirmed to be fully received at the destination, thereby preventing premature operations that could corrupt data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a predetermined latency is configured to handle worst case bridge delay, then data integrity is maintained, but overall SOC system performance is significantly reduced
Solution Approach 1:
The patent implements dynamic latency adjustment where the bridge monitor continuously observes actual bridge transfer completion times and adjusts the latency period accordingly. Instead of using a fixed predetermined latency that must account for worst-case scenarios, the system adapts the latency to match actual observed performance, thereby maintaining data integrity while minimizing performance impact.
Solution Approach 2:
The bridge monitor provides feedback about actual transfer completion timing to the system, enabling the latency period to be adjusted based on real performance data. This feedback mechanism allows the system to optimize the balance between data integrity and performance by continuously learning from actual bridge behavior rather than relying on conservative worst-case estimates.
2Productivity
If no latency is applied, then SOC system performance is maximized, but data corruption occurs due to premature assumption of transfer completion
Solution Approach 1:
The system applies a preliminary latency period after a write operation to the bridge before allowing the service device to assume completion. This preliminary waiting period ensures that the bridge has sufficient time to complete the transfer to the destination device, preventing data corruption while minimizing the delay through adaptive adjustment.
Solution Approach 2:
The patent changes the latency parameter dynamically based on observed bridge performance characteristics. The latency period is adjusted as a variable parameter rather than a fixed value, allowing the system to optimize the balance between preventing data corruption and maintaining performance by adapting to actual bridge transfer speeds and conditions.
Data Source
AI summary
A system-on-a-chip (SOC) bridge is described that applies an adapted delay, or latency, to data transfers across the bridge to avoid data corruption without reducing data transfer performance. The adapted delay assures that a source SOC service device transferring data to a destination SOC service device via the bridge and an SOC crossbar bus does not prematurely assume that the data transfer is complete upon transferring the data to the bridge. The bridge causes wait states to be inserted into the transfer between the source SOC service device and the SOC bridge until the SOC bridge receives confirmation that the data has arrived at the destination SOC service device. The adapted delay assures that subsequent operations are not prematurely initiated by the source SOC service device and/or the SOC CPU that may interfere with the data transfer from the SOC bridge to the destination SOC service device, causing corrupted data.