SoC Bridge Circuit Speculative Read for High Latency Peripherals
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Solution Overview
Problem
High latency peripheral read accesses in system-on-chip (SoC) lead to reduced overall system bandwidth due to higher access latency, causing inefficiencies as bus masters are unable to issue subsequent transactions until previous read transactions are completed, resulting in lost throughput and inactivity on high bandwidth buses.
Innovation Solution
A bridge circuit is introduced to process early read transaction requests from bus masters, converting them into low bandwidth bus requests to fetch data from low bandwidth bus slaves, which is then converted back to high bandwidth data and transferred when the scheduled read transaction is processed, allowing for simultaneous processing of read transactions and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read transactions are processed in sequential order through the bridge circuit, then data accuracy is maintained, but system bandwidth performance deteriorates due to high latency blocking the high bandwidth bus
Solution Approach 1:
The bridge circuit processes early read transaction requests before the scheduled read transaction is complete by the low bandwidth bus slave. The circuit speculatively executes the early request, converts the response to high bandwidth bus format, and stores it ready for delivery, thereby eliminating idle cycles on the high bandwidth bus while maintaining data accuracy through validation against the scheduled transaction timing
Solution Approach 2:
The bridge circuit introduces an intermediary buffering mechanism that decouples the high bandwidth bus from the low bandwidth bus timing constraints. The circuit holds early read transaction responses in intermediate storage until the scheduled transaction completes, allowing the high bandwidth bus to remain active while waiting for validation timing from the low bandwidth bus slave
2Reliability
If the high bandwidth bus waits for low bandwidth bus slave completion, then protocol compliance is maintained, but throughput is reduced due to idle cycles
Solution Approach 1:
The bridge circuit speculatively processes early read transactions before the low bandwidth bus slave completes its scheduled transaction. The circuit prepares the high bandwidth bus response in advance, maintaining protocol compliance by validating the early transaction against the scheduled completion timing, thereby eliminating idle cycles while ensuring protocol correctness
Solution Approach 2:
The high bandwidth bus maintains continuous useful action by processing early read transactions through the bridge circuit without idle cycles. The bus remains active issuing and receiving transactions while the bridge circuit manages the timing mismatch with the low bandwidth bus slave, ensuring uninterrupted data flow and maximum throughput
Data Source
AI summary
A system, circuit and method for improving system-on-chip (SoC) bandwidth performance for high latency peripheral read accesses using a bridge circuit are disclosed. In one embodiment, the SoC includes the bridge circuit, one or more bus masters, at least one high bandwidth bus slave and at least one low bandwidth bus slave that are communicatively coupled via a high bandwidth bus and a low bandwidth bus. Further, the bus masters access the at least one low bandwidth bus slave by issuing an early read transaction request in advance to a scheduled read transaction request. Furthermore, the bridge circuit receives the early read transaction request and fetches data associated with the early read transaction request. In addition, the bridge circuit receives the scheduled read transaction request. The fetched data is then sent to the bus masters upon receiving the scheduled read transaction request.