SoC Buffer Queue Allocation for Real-Time Data Stability
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Solution Overview
Problem
As the number and types of intellectual properties in application processors increase, data processing stability for real-time data becomes problematic, and overall data traffic performance is reduced.
Innovation Solution
A system on chip is designed with a buffer that dynamically reserves an area for real-time master intellectual properties based on traffic, and controls non-real-time data traffic using residual queues in the buffer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number and types of intellectual properties are increased to achieve high performance and diversification of functions, then the processing capability and functionality are improved, but data processing stability for real-time data deteriorates and overall data traffic performance is reduced
Solution Approach 1:
The buffer is segmented into multiple queues, with specific queues reserved for real-time master IPs and others for non-real-time IPs. This segmentation isolates real-time data traffic from non-real-time traffic, preventing interference and maintaining stability while supporting multiple IP types and functions.
Solution Approach 2:
Different queues within the buffer are allocated with different qualities - some queues are reserved with higher priority and guaranteed bandwidth for real-time IPs, while other queues serve non-real-time IPs with best-effort service. This local differentiation ensures real-time data processing stability while accommodating diverse functional requirements.
2Productivity
If expected output value for each intellectual property is fixedly set to be high, then the performance target is improved, but data processing stability for real-time intellectual property deteriorates
Solution Approach 1:
The buffer queue allocation is made dynamic rather than fixed. The buffer controller dynamically adjusts queue reservations and bandwidth allocation based on real-time traffic conditions and IP priorities. This allows the system to meet high output requirements while maintaining stability by adapting resource distribution to actual needs.
Solution Approach 2:
The system implements feedback mechanisms where the buffer controller monitors traffic conditions and adjusts queue allocations accordingly. This feedback loop ensures that real-time IPs receive adequate resources to maintain stability while allowing non-real-time IPs to utilize remaining capacity for high productivity.
3Reliability
If dedicated area is reserved for real-time master intellectual property in the buffer, then data processing stability is improved, but buffer utilization efficiency may deteriorate
Solution Approach 1:
The buffer queues serve multiple purposes - reserved queues provide guaranteed service for real-time IPs while also acting as priority queues that can handle overflow from non-real-time IPs when needed. Non-reserved queues primarily serve non-real-time IPs but can be dynamically allocated to real-time IPs when traffic conditions change, making the buffer structure universally applicable to different traffic scenarios.
4Productivity
If traffic control is implemented for non-real-time master intellectual property based on residual queue, then overall data traffic performance is improved, but system complexity increases
Solution Approach 1:
The buffer controller automatically performs traffic control for non-real-time IPs based on residual queue conditions without requiring complex external control mechanisms. When reserved queues have available capacity, non-real-time IPs are allowed to transmit; when reserved queues are full, non-real-time transmission is blocked. This self-service approach improves traffic performance while keeping the control logic relatively simple and integrated within the buffer controller.
Data Source
AI summary
A system on chip and a method for operating a system on chip are provided. The system on chip a plurality of intellectual property (IP) cores including a first IP core configured to process data in real-time, a buffer including a plurality of queues, and processing circuitry configured to, generate first traffic data corresponding to first data output from the first IP core, and reserve at least one queue of the plurality of queues as a first dedicated area based on the first traffic data, the first dedicated area configured to be used as a queue for transmission of the first data.