SoC Builder Automates Topology Generation
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Solution Overview
Problem
The existing methods for generating topology for System on Chip (SoC) designs are inefficient, requiring manual data entry and often result in sub-optimal designs due to the complexity of balancing bandwidth, latency, and physical hardware constraints, especially in large-scale networks with diverse traffic flows and varying channel widths.
Innovation Solution
A system and method that automatically generates optimized SoC designs by constructing SoC from functional building blocks, incorporating previously tested circuit block information, and simulating design verification, reducing manual data entry and enhancing system efficiency through automated generation of connections, domain regions, and performance reports.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If manual data entry and traditional topology generation methods are used, then design flexibility is maintained, but system efficiency and productivity are significantly reduced
Solution Approach 1:
The system automatically generates topology configurations by self-analyzing the floor plan and integration descriptions, eliminating the need for manual data entry. The automated generation module extracts necessary information from the floor plan and generates optimized topology configurations without human intervention, thereby improving productivity while maintaining design flexibility through configurable parameters.
2Manufacturing precision
If traditional topology generation methods are used, then design complexity is manageable, but manufacturing precision and optimization quality deteriorate
Solution Approach 1:
The patent replaces manual topology generation processes with an automated computer-implemented system that uses algorithms to generate optimized topology configurations. This substitution enables precise control over topology parameters and automatic validation through design check processes, improving optimization quality while managing complexity through systematic automation rather than manual methods.
Solution Approach 2:
The system incorporates a design check process that validates generated topology configurations against specified requirements and constraints. This feedback mechanism ensures that the generated topology meets optimization criteria and identifies any issues, thereby improving manufacturing precision through iterative validation and correction.
3Speed
If automated topology generation is implemented, then bandwidth and latency optimization is improved, but the complexity of balancing multiple constraints increases
Solution Approach 1:
The system automatically adjusts topology parameters such as connection configurations, routing paths, and domain region assignments to optimize bandwidth and latency performance. By programmatically changing these parameters based on floor plan analysis and integration descriptions, the system achieves performance optimization while managing constraint complexity through algorithmic approaches rather than manual trial-and-error methods.
Data Source
AI summary
Methods and example implementations described herein are generally directed to a System on Chip (SoC) design and verification system and method that constructs SoC from functional building blocks circuits while concurrently taking into account numerous chip level design aspects along with the generation of a simulation environment for design verification. An aspect of the present disclosure relates to a method for generating a System on Chip (SoC) from a floor plan having one or more integration descriptions. The method includes the steps of generating one or more connections between the integration descriptions of the floor plan based at least on a traffic specification, and conducting a design check process on the floor plan. If the design check process on the floor plan is indicative of passing the design check process, then the method generates the SoC according to the one or more connections generated between the integration descriptions.