SoC Bus Interface with Dynamic FIFO Output Position
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Solution Overview
Problem
In System-on-Chip (SoC) designs, achieving timing closure is challenging, especially for high-frequency applications and IP modules communicating with buses using request-grant validation protocols, as existing FIFO schemes complicate data loading and introduce latency issues.
Innovation Solution
A pipeline approach with a generic initiator that uses a grant-control signal from an arbiter to manage access to the bus, eliminating the need for additional FIFOs and optimizing timing closure by reducing digital path length, while employing a Moore finite-state machine to control multiplexers and buffer data effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a FIFO scheme with fixed output position is used, then timing closure is simpler, but data loading in read stage becomes more complex and shift operation loads the grant signal
Solution Approach 1:
The patent uses a dynamic output position in the FIFO buffer that can be adjusted based on the delay of the grant signal. Instead of a fixed output position, the system dynamically determines the optimal output position to balance timing requirements and data loading simplicity, thereby resolving the contradiction between timing closure simplicity and data loading complexity.
Solution Approach 2:
The system changes the parameter of output position in the FIFO buffer from a fixed value to a variable that can be adjusted according to grant signal delay characteristics. This parameter change allows the system to optimize both timing closure and data loading operations under different operating conditions.
2Ease of operation
If FIFO schemes on two locations are used to update read pointer, then pointer management is improved, but risk of injecting bugs in overflow/underflow increases
Solution Approach 1:
The patent introduces an intermediary mechanism (the dynamically determined output position and associated control logic) that mediates between the two FIFO locations and the read pointer. This intermediary layer provides additional validation and control, reducing the risk of pointer overflow/underflow bugs while maintaining ease of pointer management.
3Loss of time
If logic is placed between two parts to reduce latency, then latency is reduced, but integration problems arise for high-frequency applications
Solution Approach 1:
The patent merges the latency reduction logic directly into the FIFO buffer structure by determining the output position within the buffer itself rather than as a separate logic block. This integration approach reduces latency while avoiding the integration problems that would arise from adding separate logic between system parts.
4Productivity
If additional FIFO is used to manage continuous traffic flow, then traffic flow management is improved, but area occupation increases
Solution Approach 1:
The patent makes the existing FIFO buffer multi-functional by using it both for its primary data buffering purpose and for managing continuous traffic flow through dynamic output position determination. This eliminates the need for additional dedicated FIFO structures, thereby maintaining traffic flow management capability while reducing area occupation.
Data Source
AI summary
An interface device, such as for a System-on-Chip (SoC) bus, transfers data from an input queue through an output to a target. The interface device includes a buffer network for buffering input data when the target is not available for receiving the data. A multiplexer switches between a first operating condition for directing to the target the data from the input queue, and a second operating condition for directing to the target the buffered data from the buffer network. A finite-state machine selectively switches the multiplexer between the first operating condition and the second operating condition based on an acknowledgement signal received from the target. This indicates the availability of the target for receiving the data.