SoC Bus Isolation Logic for Voltage and Timing Faults
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Solution Overview
Problem
In integrated circuits (ICs) configured as a system on a chip (SoC), communication between functional units in different power domains is inhibited when one domain is powered down, posing a challenge in maintaining operation of high-performance interfaces during power failures or timing errors.
Innovation Solution
The implementation of detection logic in a first voltage domain to isolate communication via a communication bus upon detecting voltage or timing errors, utilizing a combination of hardware and software responses to ensure robust logic and electrical isolation between domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If functional units in different power domains are interconnected without isolation mechanisms, then communication between domains is maintained, but the system becomes vulnerable to voltage errors and timing errors propagating across domains
Solution Approach 1:
The patent introduces isolation logic as an intermediary component between voltage domains that mediates communication signals. This isolation logic detects voltage and timing errors and selectively blocks or passes signals, acting as a mediator that protects the system while maintaining normal communication functionality.
Solution Approach 2:
The isolation logic continuously monitors communication signals for voltage errors and timing errors, using feedback mechanisms to detect anomalies and dynamically adjust signal transmission. When errors are detected, the feedback loop triggers isolation actions to prevent error propagation while allowing normal operation when no errors are present.
2Reliability
If isolation logic is implemented to detect and respond to voltage errors, then error propagation is prevented, but the response time and system complexity increase
Solution Approach 1:
The isolation logic is pre-configured with detection capabilities for voltage errors and timing errors, establishing isolation mechanisms in advance rather than reacting after errors occur. This preliminary setup allows for rapid detection and response when errors actually occur, minimizing response time.
Solution Approach 2:
The system divides the SoC into separate voltage domains with isolation logic positioned between them, creating segmented error containment zones. This segmentation allows errors to be detected and isolated locally without affecting the entire system, enabling faster localized response times.
3Productivity
If high-performance interfaces operate across voltage domains during power failures, then interface performance is maintained, but timing errors and voltage instability increase
Solution Approach 1:
The isolation logic dynamically adjusts its operation based on real-time detection of timing errors and voltage conditions. It can selectively isolate specific signal paths while allowing others to continue operating, dynamically balancing performance maintenance with error prevention based on current system conditions.
Data Source
AI summary
In described examples, an SoC includes at least two voltage domains interconnected with a communication bus. Detection logic in a first voltage domain determines when a voltage error occurs in a second voltage domain and isolates communication via the communication bus when a voltage error or a timing error is detected.