SoC Cache Partitioning for Inter-Cluster Memory Communication

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Solution Overview

Problem

The efficient utilization of cache in System on Chip (SoC) under multi-core architecture has not been fully explored, limiting its application in scenarios requiring high-speed information processing.

Innovation Solution

Configuring partial storage space of the cache as a cluster memory for communication between clusters in the SoC, allowing peer-to-peer and broadcast communication among clusters, and utilizing cluster memory for operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If cache is used for traditional single-core operations, then cache hit rate is maintained, but cache utilization under multi-core architecture is insufficient

Engineering Contradiction:

Improvecache adaptability to multi-core architectureVSAvoidcache utilization efficiency

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The cache is configured to serve dual purposes: traditional L3 caching for individual cores and cluster memory for inter-cluster communication. This multi-functional configuration allows the same hardware resource to support both traditional caching operations and new cluster-based parallel operations, resolving the contradiction between adaptability and utilization efficiency

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Speed

If cache storage space is allocated for cluster memory operations, then information transfer efficiency among clusters is improved, but cache hit rate for traditional caching may be affected

Engineering Contradiction:

Improveinformation transfer speed among clustersVSAvoidcache hit rate

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The cache storage space is segmented into distinct regions: cluster memory portion for inter-cluster communication and traditional L3 cache portion for core-level caching. This segmentation allows both functions to operate simultaneously with dedicated resources, ensuring high-speed cluster communication while maintaining reliable cache hit rates for traditional operations

Inventive Principle:

Principle #1Segmentation

3Productivity

If full cache space is used for cluster operations, then cluster communication efficiency is maximized, but cache availability for individual core operations is reduced

Engineering Contradiction:

Improvecluster operation efficiencyVSAvoidcache availability for different operations

Core Design Contradiction:

ProductivityVSAdaptability or versatility

Solution Approach 1:

Different portions of the cache are assigned different qualities/functions: the cluster memory portion is optimized for high-speed inter-cluster data transfer, while the L3 cache portion maintains traditional caching characteristics for core operations. This local differentiation resolves the contradiction by allowing each region to be optimized for its specific purpose while sharing the same physical cache hardware

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20250341981A1Method for system on chip, and related product thereof

Publication Date: 2025.11.06 CAMBRICON (XIAN) SEMICON CO LTD

AI summary

The present disclosure relates to a method for a system on chip, the system on chip, an integrated circuit device, a board card, and a computing apparatus, where the computing apparatus is included in a combined processing apparatus that further includes an interface apparatus and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a user specified computation operation. The combined processing apparatus further includes a storage apparatus. The storage apparatus is connected to the computing apparatus and other processing apparatus, respectively. The storage apparatus is used to store data of the computing apparatus and other processing apparatus.